P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1919-1924 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Power Supply Voltage ◽  
Flip Flop ◽  
Nanometer Cmos ◽  
P Type ◽  
Cmos Processes

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1930-1936 ◽  
Author(s):  
Jian Ping Hu ◽  
Li Fang Ye ◽  
Li Su
Keyword(s):  
Power Dissipation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Total Power ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
P Type ◽  
Cmos Processes

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

2010 ◽  
Vol 159 ◽  
pp. 155-161
Author(s):  
Jin Tao Jiang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Gate Structure ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
P Type ◽  
Cmos Processes

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

scholarly journals Implementation of Face Recognition Processing Using an Embedded Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 428-436 ◽  
Author(s):  
Hiroyuki Kondo ◽  
◽  
Masami Nakajima ◽  
Miroslaw Bober ◽  
Krzysztof Kucharski ◽  
...  
Keyword(s):  
Face Recognition ◽  
Power Consumption ◽  
High Performance ◽  
Supply Voltage ◽  
Chip Multiprocessor ◽  
Low Power Consumption ◽  
Single Chip ◽  
Power Supply Voltage ◽  
Embedded Processor ◽  
Tremendous Amount

Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS

2014 ◽  
Vol 23 (06) ◽  
pp. 1450088 ◽  
Author(s):  
LEONARDO PANTOLI ◽  
VINCENZO STORNELLI ◽  
GIORGIO LEUZZI
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Bandpass Filter ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filters ◽  
Center Frequency ◽  
Power Supply Voltage ◽  
Microwave Applications

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

Integral Type Multi-Ramp for Single-Slope ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1908-1912 ◽  
Author(s):  
Nan Lyu ◽  
Ning Mei Yu ◽  
He Jiu Zhang
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Supply Voltage ◽  
High Accuracy ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Voltage Reference ◽  
Integral Type ◽  
Power Supply Voltage ◽  
The One

This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.

scholarly journals A Review on Energy Efficient CMOS Digital Logic

2013 ◽  
Vol 3 (6) ◽  
pp. 552-561 ◽  
Author(s):  
B. L. Dokic
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Power Supply ◽  
Digital Circuits ◽  
Supply Voltage ◽  
Digital Logic ◽  
Power Supply Voltage ◽  
Operating Modes ◽  
Optimum Choice ◽  
Adiabatic Logic

Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

A SELECTIVE REPLACEMENT METHOD FOR TIMING-ERROR-PREDICTING FLIP-FLOPS

2012 ◽  
Vol 21 (06) ◽  
pp. 1240013 ◽  
Author(s):  
YUJI KUNITAKE ◽  
TOSHINORI SATO ◽  
HIROTO YASUURA ◽  
TAKANORI HAYASHIDA
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Large Area ◽  
Power Supply Voltage ◽  
Timing Error ◽  
Large Power ◽  
Technology Scaling ◽  
Replacement Method ◽  
Area Overhead ◽  
Spatial Redundancy

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. The design margin in the supply voltage will be overestimated, which results in large power consumption. To eliminate the waste power consumption due to the overestimated power supply voltage, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named Canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

scholarly journals CMOS Realization of Fully Electronically Tunable Single Resistance Control Mixed Mode Biquad Filter Employing Single VDTA at ± 0.6V

2021 ◽  
Vol 20 ◽  
pp. 48-57
Author(s):  
Ghanshyam Singh ◽  
Hameed Pasha ◽  
H. C. Hadimani ◽  
Zuleka Tabbusm
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mixed Mode ◽  
Supply Voltage ◽  
Low Power Consumption ◽  
Pass Band ◽  
Power Supply Voltage ◽  
Passive Element ◽  
Biquad Filter ◽  
Filter Configuration

This paper presents a single resistance control single VDTA based Mixed Mode type Biquad filter. The proposed Transadmittance Mode (TAM) type Biquad filter configuration employed single voltage differencing transconductance amplifier (VDTA) as an active building block, three passive element namely one grounded resistor, one grounded capacitor and one floating capacitor. The proposed transadmittance Mode multifunction Biquad filter configuration is presenting transadmittance mode type four basic standard filter functions low pass, high pass, band pass, band reject or band stop or band eliminate filter responses. These four type filter responses are realizing simultaneously with the selection of single input voltage signal. The proposed Transadmittance Mode multifunction Biquad filter configuration has more advantageous features such as low active and passive sensitivities, low power supply voltage, low power consumption, low quality factor, very low power consumption, more electronic tunability, higher linearity and required small area of the chip. The performance of the proposed configuration has been verified through PSPICE simulation using 0.18μm CMOS Technology process parameters.

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

2018 ◽  
Vol 27 (10) ◽  
pp. 1850160 ◽  
Author(s):  
Manoj Kumar ◽  
Dileep Dwivedi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Supply Voltage ◽  
Back Gate ◽  
Tuning Method ◽  
Low Power Cmos ◽  
Improved Performance ◽  
Mos Varactor

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying the output load capacitance with the use of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage ([Formula: see text] and back-gate voltage ([Formula: see text]. Variation of [Formula: see text] from 1[Formula: see text]V to 2[Formula: see text]V provides the frequency deviation from 1.970[Formula: see text]GHz to 1.379[Formula: see text]GHz with I-MOS width of 8 [Formula: see text]m at power supply voltage ([Formula: see text] of 1.8[Formula: see text]V. Power consumption of the circuit is 1.296[Formula: see text]mW with [Formula: see text] of 1.8[Formula: see text]V. The results have been obtained for different I-MOS varactor widths like 5[Formula: see text][Formula: see text]m, 8[Formula: see text][Formula: see text]m and 10[Formula: see text][Formula: see text]m. Further, variations in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the Vdd variation from 1[Formula: see text]V to 3[Formula: see text]V. In addition, by variations of [Formula: see text] from 0[Formula: see text]V to 1.8[Formula: see text]V and [Formula: see text] from 1[Formula: see text]V to 3[Formula: see text]V, the proposed oscillators operate in the frequency range from 0.556[Formula: see text]GHz to 2.584[Formula: see text]GHz for 8[Formula: see text][Formula: see text]m width of I-MOS varactor. Proposed VCO circuit show a phase noise of [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the carrier frequency and the figure of merit (FoM) for the VCO is 154.51[Formula: see text]dB/Hz. Proposed VCO shows an improved performance in terms of power consumption, output frequency and FoM.

Sign in / Sign up

Export Citation Format

Share Document