Low power CMOS digital circuit design methodologies with reduced voltage swing

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

Download Full-text

Low power digital circuit design

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat No 04EX850) ESSDER-04 ◽

10.1109/essder.2004.1356476 ◽

2004 ◽

Cited By ~ 7

Author(s):

T. Sakurai

Keyword(s):

Low Power ◽

Circuit Design ◽

Digital Circuit ◽

Digital Circuit Design

Download Full-text

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v8.i3.pp162-168 ◽

2019 ◽

Vol 8 (3) ◽

pp. 162

Author(s):

Pritty Pritty ◽

Manoj Kumar ◽

Mariyam Zunairah

Keyword(s):

Power Consumption ◽

Low Power ◽

Circuit Design ◽

Power Dissipation ◽

Full Adder ◽

Digital Circuit ◽

Xor Gate ◽

Digital Circuit Design ◽

Result Show ◽

Body Bias

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Download Full-text

Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.a1623.059120 ◽

2020 ◽

Vol 9 (1) ◽

pp. 465-473

Keyword(s):

Low Power ◽

Circuit Design ◽

Power Dissipation ◽

Digital Circuit ◽

Logic Circuits ◽

Digital Circuit Design ◽

Adiabatic Logic ◽

Low Power Dissipation ◽

In Series ◽

Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

Download Full-text