DEVELOPMENT OF CALIBRATION MODULES FOR A COMPLEX OF ASSESSING THE IMPACT OF ELECTROMAGNETIC INTERFERENCE ON ELECTRONIC DEVICES

2022 ◽  
pp. 95-99
Author(s):  
Д.А. Пухов ◽  
А.В. Суворин ◽  
Д.В. Васильченко ◽  
М.А. Ромащенко
Keyword(s):  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Mutual Influence ◽  
Circuit Board ◽  
Modern World ◽  
Signal Distortion ◽  
Printed Circuit ◽  
Hardware Complex ◽  
Software And Hardware ◽  
The Impact

В современном мире при стремлении человечества к миниатюризации электротехнической и радиоэлектронной продукции без потери технических характеристик устройств, наряду с их расширением одной из значимых проблем является влияние электромагнитных помех на стабильное функционирование устройств. Представлены модули калибровки, используемые в программно-аппаратном комплексе (ПАК), который позволяет произвести оценку влияния электромагнитных помех (ЭМП) на электронные средства. Практическое искажение сигналов неизбежно, так как причиной помех может стать взаимное влияние элементов печатной платы (ПП) друг на друга, а также конфигурация самого рисунка дорожек ПП и её топологии. Рассматриваются модули, позволяющие выявить ряд ошибок по ранее полученным результатам и обеспечить калибровку комплекса с целью повышения точности оценки влияния самоиндукции и импеданса линии передач на вносимые искажения сигнала при различных конфигурациях трассировки печатной платы. Применение данного программно-аппаратного комплекса позволяет значительно сократить время, необходимое на разработку устройства и комплекс испытаний, что, в свою очередь, снижает финансовую нагрузку на выпуск единицы продукции, поскольку позволяет выявить недостатки устройств на стадии макетирования электротехнической продукции In the modern world, with the desire of all mankind to miniaturize electrical products without loss of power, one of the significant problems is the influence of electromagnetic interference on the stable functioning of devices. This article presents the calibration modules used in the software and hardware complex (SHC), which allows one to assess the influence of electromagnetic interference (EMI) on electronic means. The practical distortion of signals is inevitable since the cause of interference can be their mutual influence on each other, as well as the configuration of the printed circuit board pattern itself. The paper considers modules that allow identifying a number of errors based on previously obtained results and providing calibration of the complex in order to increase the accuracy of estimating the effect of self-induction and transmission line impedance on the introduced signal distortion in various configurations of the PCB trace. The use of this software and hardware complex can significantly reduce the development time and conduct tests that require financial costs since it allows one to conduct a number of experiments at the stage of prototyping electrical products

INTERFACE MODULE DEVELOPMENT FOR SOFTWARE AND HARDWARE COMPLEX OF AUTOMATIC TEXTS CLASSIFICATION

2020 ◽  
pp. 38-48
Author(s):  
Golub Tetiana ◽  
◽  
Zeleneva Irina ◽  
Hrushko Svitlana ◽  
Kotenko Artem
Keyword(s):  
Printed Circuit Board ◽  
Operating Conditions ◽  
Circuit Board ◽  
Local Network ◽  
Design System ◽  
Printed Circuit ◽  
Interface Module ◽  
Hardware Complex ◽  
Software And Hardware ◽  
Automatic Text

The amount of information presented in text form is constantly increasing. A feature of a large amount of such information in most cases is the lack of its structuredness, which complicates the analysis process. At the stage of document processing in the information and analytical system, an automatic classifier is used – as a program, or as a software and hardware complex that accelerates automatic text processing. In this paper, a software and hardware complex is considered, in which the software part functions on the user's computer, and the hardware part is implemented on the FPGA. Thus, the problem of organizing the connection between its two parts is urgent. While FPGAs have high internal parallelism and very high internal bandwidth, the low bandwidth of the interface between the accelerator and the rest of the system, as well as restrictions on the conditions of its use, is a bottleneck in the field of data transfer. This problem is aggravated in the conditions of the need to create a network system for constructing a classifier, where several user computers connected to the network need access to the hardware-implemented part of the complex (accelerator). The aim of this work is to develop an internal interface module with network communication, in accordance with the technical and functional requirements of the software and hardware complex for automatic text classification. Considering the need to provide network access to the accelerator, as a result of the analysis, the Fast Ethernet interface was chosen as the base one. This interface is the most common LAN standard used by most businesses. For the development of the printed circuit board of the interface module, a comprehensive computer-aided design system Altium Designer was used. After the development of the electrical schematic diagram of the project, a simulation of the controller part was created in the Proteus digital-to-analog simulation program. For the convenience of testing the developed interface module, the Arduino UNO module and the SPI serial interface were used. A feature of the developed module is the support of network-level protocols, it makes it possible to organize access from any personal computer of the local network to an expansion board built on the basis of FPGA. The developed printed circuit board of the interface module was analyzed for possible defects and a list of recommendations for the operating conditions of the device was developed. The interface board is designed taking into account the balanced ratio of price-performance criteria, and is intended for use in any institution where there is a need for automatic classification of text documents.

Numerical Simulation and Experimental Measurement of a Printed Circuit Board Subjected to Drop Test

2009 ◽  
Vol 419-420 ◽  
pp. 37-40
Author(s):  
Shiuh Chuan Her ◽  
Shien Chin Lan ◽  
Chun Yen Liu ◽  
Bo Ren Yao
Keyword(s):  
Finite Element ◽  
Experimental Measurement ◽  
Test Specimen ◽  
Printed Circuit Board ◽  
Drop Impact ◽  
Simulation Technique ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit ◽  
The Impact

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.

Research on Liberation Mechanism of the Impact Crushing Waste Printed Circuit Board

2010 ◽  
Vol 113-116 ◽  
pp. 730-734 ◽  
Author(s):  
Chen Long Duan ◽  
Yue Min Zhao ◽  
Jing Feng He ◽  
Nian Xin Zhou
Keyword(s):  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Distribution Model ◽  
Evaluation Indexes ◽  
Printed Circuit ◽  
Waste Printed Circuit Boards ◽  
Waste Printed Circuit Board ◽  
Impact Crushing ◽  
The Impact

The reutilization of waste Printed Circuit Boards (PCB) is a focused topic in the field of environment protection and resource recycling, and the crushing is the crucial process for recycling waste PCB. A hamper impacting crusher was used to achieve metals crushing liberation from non-metals, the liberation mechanism of PCB can be explained by dispersion liberation accompanied disengaging liberation. The Rosin-Rammler distribution model of crushed PCB particle was put forward. The evaluation indexes show that Rosin-Rammler function can accurately describe size distribution of PCB particles because the convergence property R2 is 0.99694 and fitting error E is 4.80658. The selective crushing is appearance with metals concentrated in coarser fraction and non-metals in finer size during comminution processing. The impact crushing is an effective method to metals liberation of PCB particles.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Nonlinear Response of a Printed Circuit Board in Shock

2009 ◽  
Author(s):  
M. Vujosevic ◽  
P. Raghavan ◽  
G. Ramanathan ◽  
W. Hezeltine ◽  
K. Blue
Keyword(s):  
Printed Circuit Board ◽  
Transfer Functions ◽  
Numerical Approach ◽  
Circuit Board ◽  
Special Importance ◽  
Strain Measurements ◽  
Printed Circuit ◽  
Numerical Finite Element ◽  
Nonlinear Deformations ◽  
The Impact

This work focuses on deformation mechanisms taking place in a Printed Circuit Board (PCB) exposed to high impact shock. A combined experimental, theoretical, and numerical approach has been applied to address both the nature of the observed deformation and its modeling and test metrology implications. Experimental evidence overwhelmingly indicates that a PCB in both test and system applications undergoes nonlinear deformations. Geometric nonlinearity of board response is attributed to the elevated in-plane (membrane) stresses that develop when a drop height and/or inertia forces are significant. The impact of these stresses on deformations (board strain) was quantified using a specially designed test. Membrane stresses were also accounted for in a numerical (Finite Element Method) model developed and carefully validated in the course of this study. The model shows a very good agreement with test data. The nonlinearity of PCB deformation in shock, i.e. the fact that both bending moments and in-plane forces are present in the board has important implications on test metrology development and on correlation between the measured board strain and stresses in interconnects of surface mounted components. Of special importance is the impact that nonlinearity can have on development of transfer functions between strain measurements on system boards and strain measurements on test boards, which is also addressed in the paper.

scholarly journals Design and Study of a Wide-Band Printed Circuit Board Near-Field Probe

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2201 ◽  
Author(s):  
Pedro A. Martinez ◽  
Enrique A. Navarro ◽  
Jorge Victoria ◽  
Adrian Suarez ◽  
Jose Torres ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Transmission Loss ◽  
Near Field ◽  
Fem Simulation ◽  
Numerical Results ◽  
Circuit Board ◽  
Frequency Range ◽  
Printed Circuit

Magnetic near-field probes (NFP) represent a suitable tool to measure the magnetic field level from a small electromagnetic interference (EMI) source. This kind of antenna is useful as a magnetic field probe for pre-compliance EMC measurements or debugging tasks since the user can scan a printed circuit board (PCB) looking for locations with strong magnetic fields. When a strong H-field point is found, the designer should check the PCB layout and components placement in that area to detect if this could result in an EMI source. This contribution focuses on analyzing the performance of an easy to build and low-cost H-field NFP designed and manufactured using a standard PCB stack-up. Thereby, the frequency range and sensitivity of the NFP-PCB are analyzed through a Finite Element Method (FEM) simulation model that makes it possible to evaluate its sensibility and effective frequency range. The numerical results obtained with the FEM models are validated against measurements to verify the design and performance of our NFP. The FEM model reproduces the experimental procedure, which is used to evaluate the performance of the NFP in terms of sensitivity by means of the simulated near-field distribution. The NFP-PCB has almost a flat response from 180 MHz to 6 GHz, with an almost perfect concordance between numerical and experimental S21 results. The numerical results show an average transmission loss of −27.9 dB by considering the flat response bandwidth, whereas the experimental one is −29.7 dB. Finally, the designed NFP is compared to two high-quality commercial probes in order to analyze its performance.

An Assessment of the Impact of Interconnect Strategies on Thermal Performance of GaAs Power Amplifier IC Devices

2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Wire Bond ◽  
Die Attach ◽  
The Impact

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.

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