scholarly journals Effect of Epoxy Molding Compound Material and Roughness Leadframe to Integrated Circuit Package for Automotive Devices

2020 ◽  
Vol 18 (2) ◽  
pp. 179-188
Author(s):  
Anan Sukantharat ◽  
Kessararat Ugsornrat ◽  
Chalermsak Sumithpibul
Keyword(s):  
Integrated Circuit ◽  
Coefficient Of Thermal Expansion ◽  
Type A ◽  
Type B ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Material Type ◽  
Compound Material ◽  
Cte Mismatch ◽  
Compound Materials

This research studied about an effect of epoxy molding compound material and roughness leadframe of integrated circuit package for automotive device. In manufacturing process, the epoxy molding compound material and leadframe roughness are main factors that effect to coefficient of thermal expansion (CTE) and reliability for automotive device package with no delamination in high temperature application. In experiment, two types of epoxy molding compound materials were studied and compared between standard and roughened leadframe for quad flat non lead (QFN) package. For reliability test, the epoxy molding compound materials type A and type B with different leadframe were analyzed with moisture sensitivity level 1 to observe delamination inside packages. The results showed that CTE of epoxy molding compound material type A is less CTE mismatch than that of epoxy molding compound material type B with both standard and roughness leadframe. Moreover, the results also found no delamination for epoxy molding compound material type A with roughened leadframe. In addition, both epoxy molding compound materials showed significant delamination inside packages with standard leadframe.

scholarly journals Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

2017 ◽  
Vol 901 ◽  
pp. 012090 ◽  
Author(s):  
Jirayu Tachapitunsuk ◽  
Kessararat Ugsornrat ◽  
Warayoot Srisuwitthanon ◽  
Panakamon Thonglor
Keyword(s):  
Aging Time ◽  
Integrated Circuit ◽  
Molding Process ◽  
Epoxy Molding Compound ◽  
Molding Compound

Preparation of Hexaphenylamine Cyclotriphosphazene and its Green Flame Retardance on Epoxy Molding Compound for Large-Scale Integrated Circuit Packaging

2011 ◽  
Vol 239-242 ◽  
pp. 1386-1390
Author(s):  
Ming Shan Yang ◽  
Lin Kai Li
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Flame Retardants ◽  
Large Scale ◽  
Reaction Rate ◽  
Flame Retardance ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Synthesis Parameters ◽  
Halogen Free

The hexaphenylamine cyclotriphosphazene (HPACTPZ) was synthesized using titrating technology of hexachlorocyclotriphosphazene solution and the synthesis parameters were investigated, and the structure of HPACTPZ was analyzed by FTIR and NMR in this paper. Using HPACTPZ synthesized in the work as flame retardant, the epoxy molding compound(EMC) for packaging of large-scale integrated circuits with halogen-free flame retardance was prepared. The results have shown that the flame retardance of EMC flame-retardanced by HPACTPZ was up to UL 94 V0 rating(3.2mm) and the oxygen index of the EMC was up to 35.8%, which indicates that HPACTPZ has much better flame retardance for EMC than traditional halogen flame-retardants. Meanwhile, HPACTPZ accelerated the curing reaction rate of EMC, which can be used for manufacturing the quick-curing EMCs or afterward-curing-free EMCs.

Synthesis of Phosphazene Flame Retardant and its Application in Epoxy Molding Compound for Large-Scale Integrated Circuit Packaging

2011 ◽  
Vol 216 ◽  
pp. 474-478 ◽  
Author(s):  
Ming Shan Yang ◽  
Jian Wei Liu ◽  
Lin Kai Li
Keyword(s):  
Integrated Circuits ◽  
Flame Retardant ◽  
Integrated Circuit ◽  
Flame Retardants ◽  
Large Scale ◽  
Flame Retardance ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Synthesis Parameters ◽  
Halogen Free

The tri(o-phenylenediamine) cyclotriphosphazene (TPCTP) was synthesized using titrating technology of hexachlorocyclotriphosphazene solution and the synthesis parameters were investigated, and the structure of TPCTP was analyzed by FTIR in this paper. Using TPCTP synthesized in the work as flame retardant, the epoxy molding compound(EMC) for packaging of large-scale integrated circuits with halogen-free flame retardance was prepared. The results have shown that the flame retardance of EMC flame-retardanced by TPCTP was up to UL 94 V0 rating(1.6mm) and the oxygen index of the EMC was up to 34.5%, which indicates that TPCTP has much better flame retardance for EMC than traditional halogen flame-retardants. Meanwhile, TPCTP accelerated the curing reaction rate of EMC, which can be used for manufacturing the quick-curing EMCs or afterward-curing-free EMCs.

Siloxane Modified Polyimides for Microelectronics Coating Applications

1998 ◽  
Vol 10 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Yasuharu Yamada
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Devices ◽  
Type A ◽  
Dielectric Constants ◽  
Block Type ◽  
Type B ◽  
Coating Properties ◽  
Adhesive Properties ◽  
Coating Materials ◽  
Polymer Backbone

Two types of siloxane modified polyimide were prepared as coating materials for microelectronics applications and their thermal, mechanical, electrical, adhesive and coating properties were characterized. The coatings prepared were classified as polysiloxane block (type A) polyimides and disiloxane modified (type B) polyimides. All of the polyimides showed excellent thermal, mechanical, electrical, adhesive and coating properties suitable for use in microelectronics coating applications. The type A polyimides have lower dielectric constants and good stress relaxation capability as compared with typical aromatic polyimides. The type B polyimides have excellent adhesive properties to silicon wafers. The polyimide prepared from 2, 2-bis[4-aminophenoxyphenyl]hexafluoropropane exhibited the lowest dielectric constant due to the presence of trifluoromethyl groups in the polymer backbone. Model encapsulated semiconductor devices coated with various polyimides were assembled, and the interface adherence between the polyimide and the encapsulant along with the reliability of the semiconductor devices were examined. Superior interface adherence between the polyimide passivant and the encapsulant was exhibited, resulting in improved reliability of integrated circuit chips. With the incorporation of siloxane moieties into the polyimide backbone these siloxane modified polyimides were shown to be good candidate materials for microelectronics coatings.

scholarly journals The Evaluation of Durability of Plasma-Sprayed Thermal Barrier Coatings with Double-layer Bond Coat

Coatings ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 241 ◽  
Author(s):  
Li ◽  
Peng ◽  
Dong ◽  
Zhou ◽  
Wang ◽  
...  
Keyword(s):  
Thermal Barrier Coatings ◽  
Double Layer ◽  
Bond Coat ◽  
Coefficient Of Thermal Expansion ◽  
Type A ◽  
Thermal Barrier ◽  
Type B ◽  
Barrier Coatings ◽  
Oxidation Layer ◽  
Plasma Sprayed

The durability of atmospheric plasma-sprayed thermal barrier coatings (APS TBCs) with a double-layer bond coat was evaluated via isothermal cycling tests under 1120 °C. The bond coat consisted of a porosity layer deposited on the substrate and an oxidation layer deposited on the porosity layer. Two types of double-layer bond coats with different thickness ratios of the porosity layer to the oxidation layer (type A: 1:2 and type B: 2:1, respectively) were prepared. The results show that the porosity layer was oxidation free, the oxidation layer included a fraction of well-distributed α-Al2O3. The coefficient of thermal expansion of the oxidation layer was about 11.2 × 10−6 K−1, which was rather lower than that of the porosity layer. Thus, the oxidation layer can be regards as a secondary bond coat between ceramic topcoat and traditional bond coat. The thermal cyclic lifetime of type A TBCs was about 60 cycles, which exceeded 1.2 times the durability of type B TBCs. The delamination cracks in both TBCs all propagated in the ceramic topcoat, which were all identical to those in traditional TBCs. Therefore, the design of the double-layer bond coat affected the stress level rather than the stress distribution in TBCs.

Effect of Polymer Liners in Different Via Shapes: Impact on Crosstalk Induced Delay

2021 ◽  
Author(s):  
Maya Chandrakar ◽  
Manoj Kumar Majumder
Keyword(s):  
Integrated Circuit ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Network ◽  
Worst Case ◽  
Liner Material ◽  
Low Dielectric ◽  
Aspect Ratios ◽  
Cte Mismatch ◽  
Metal Liner ◽  
The Impact

Abstract The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material SiO2 is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 nm and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T-type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

2010 ◽  
Vol 132 (1) ◽  
Author(s):  
Hu Guojun ◽  
Andrew A. O. Tay ◽  
Luan Jing-En ◽  
Ma Yiyi
Keyword(s):  
Thermal Expansion ◽  
Material Properties ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Element Analysis ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Interface Delamination ◽  
Underfill Material ◽  
Die Thickness

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

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