Silicide Applications In Microelectronics

1981 ◽  
Vol 10 ◽  
Author(s):  
Billy L. Crowder
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Device Structures ◽  
Direct Replacement ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Scale Integration

ABSTRACTThe advent of very-large-scale integration in microelectronics has been achieved by reduction in lithographic dimensions coupled with a corresponding decrease in vertical dimensions in properly scaled device structures. This development has placed severe demands upon interconnection technology. The practice of using semiconducting regions (diffusions or polycrystalline silicon) for interconnecting devices is no longer viable because of the high resistance associated with such regions (i.e. interconnections do not “scale” properly). One solution to this problem is the use of multilevel metallization, but this requires tens of thousands of small contacts to shallow diffusions. Refractory metals such as titanium are being explored as materials which provide the necessary stable low resistance contacts suitable for integrated circuit applications. Another solution to the problem is to develop a higher conductivity material to replace or supplement polycrystalline silicon. Refractory metal disilicides have been extensively investigated for this application -both as a direct replacement for polycrystalline silicon or in a silicide/polycrystalline silicon composite (polycide). A critical review of the present status in both these areas will be presented. Emphasis will be upon our experience gained in conjunction with the development of a 1 μm silicon gate metal/oxide/ semiconductor field effect transistor technology.

Design of bilayer graphene nanoribbon tunnel field effect transistor

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ramesh Kumar Vobulapuram ◽  
Javid Basha Shaik ◽  
Venkatramana P. ◽  
Durga Prasad Mekala ◽  
Ujwala Lingayath
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Graphene Nanoribbons ◽  
Content Type ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
A New Technique ◽  
Scale Integration

Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs). Design/methodology/approach To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism. Findings The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET. Originality/value This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

scholarly journals Vlsi Interconnection Modelling Using a Finite Element Approach

1995 ◽  
Vol 18 (3) ◽  
pp. 179-202
Author(s):  
Umesh Kumar
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Low Complexity ◽  
Stratified Medium ◽  
Base Function ◽  
Large Scale Integration ◽  
Element Approach ◽  
Scale Integration ◽  
High Degree ◽  
Important Shift

In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.

scholarly journals Unbalanced-Tests to the Improvement of Yield and Quality

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3032
Author(s):  
Chung-Huang Yeh ◽  
Jwu-E Chen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Manufacturing Industry ◽  
Product Distribution ◽  
Test Method ◽  
Distribution Model ◽  
Threshold Test ◽  
Yield And Quality ◽  
Large Scale Integration ◽  
Scale Integration

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.

scholarly journals A Graphene/Polycrystalline Silicon Photodiode and Its Integration in a Photodiode–Oxide–Semiconductor Field Effect Transistor

Micromachines ◽  
2020 ◽  
Vol 11 (6) ◽  
pp. 596
Author(s):  
Yu-Yang Tsai ◽  
Chun-Yu Kuo ◽  
Bo-Chang Li ◽  
Po-Wen Chiu ◽  
Klaus Y. J. Hsu
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Image Sensor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Silicon Photodiode ◽  
Effect Transistor ◽  
Logarithmic Dependence

In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics of a graphene/polycrystalline silicon junction and explores one possible usage of the junction. The current–voltage curve of the junction was measured to show the typical exponential behavior that can be seen in a forward biased diode, and the photovoltage of the junction showed a logarithmic dependence on light intensity. A new phototransistor named the “photodiode–oxide–semiconductor field effect transistor (PDOSFET)” was further proposed and verified in this work. In the PDOSFET, a graphene/polycrystalline silicon photodiode was directly merged on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET). The magnitude of the channel current of this phototransistor showed a logarithmic dependence on the illumination level. It is shown in this work that the PDOSFET facilitates a better pixel design in a complementary metal–oxide–semiconductor (CMOS) image sensor, especially beneficial for high dynamic range (HDR) image detection.

Sign in / Sign up

Export Citation Format

Share Document