Calculation of External Resistance of Two Gates' Circuits Connected with Different Loads

2013 ◽  
Vol 722 ◽  
pp. 18-22
Author(s):  
Yu Qiong Shan ◽  
Chang Ji Shan ◽  
Jun Luo ◽  
Xiao Pan Li ◽  
Li Zhou
Keyword(s):  
Output Port ◽  
Proper Choice ◽  
Nand Gate ◽  
External Resistance ◽  
Gate Circuit ◽  
Nor Gate ◽  
Output Information ◽  
Do So

The TTL nand gate cannot be directly connected with the output port of two gates to set a relationship with their output information while the integrated open-collector nand gate can do so by making a proper choice of between the integrated open-collector lines and the resistances.This paper aims to analyze the calculation of, Rp, the externally connected resistance of integrated gate circuit which is made up of open-collector gate, and open-drain gate when the and-not gate, and nor gate of the Loaded gates are discussed respectively.

Titanium Oxide Memristor Based Digital Encoder Circuit

2014 ◽  
Vol 644-650 ◽  
pp. 3430-3433
Author(s):  
Yue Wei Hou ◽  
Xin Xu ◽  
Wei Wang ◽  
Xiao Bo Tian ◽  
Hai Jun Liu
Keyword(s):  
Titanium Oxide ◽  
Logic Gate ◽  
Logic Circuits ◽  
Practical Approach ◽  
Nand Gate ◽  
Gate Circuit

Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.

scholarly journals Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 1521-1525
Keyword(s):  
Dynamic Logic ◽  
Vlsi Design ◽  
Full Adder ◽  
Higher Order ◽  
The Self ◽  
Gate Circuit ◽  
Carry Select Adder ◽  
Nor Gate ◽  
Reduction In Area

Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructed with 10 transistors based on the optimization of truth tale of a full adder. A 3 transistor X-NOR gate circuit is also used instead of a conventional X-NOR circuit in the self checking path. Adders of size 4 bit and 8 bit are constructed in various technologies. The results show that the proposed structure reduces the transistor over head by almost 47% and 46% for 4bit and 8bit structures respectively. By achieving this much of reduction in area this work could be suggested for higher order VLSI structures like BIST,DCT etc.,

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

Instability changes the MAGIC NAND gate to the NOR gate

2019 ◽  
Author(s):  
Xi Zhu ◽  
Hongchang Long ◽  
Zhiwei Li ◽  
Hui Xu ◽  
Haijun Liu ◽  
...  
Keyword(s):  
Nand Gate ◽  
Nor Gate

scholarly journals FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1344
Author(s):  
Liu Yang ◽  
Yuqi Wang ◽  
Zhiru Wu ◽  
Xiaoyuan Wang
Keyword(s):  
Circuit Design ◽  
Logic Circuit ◽  
Nand Gate ◽  
Simulation Research ◽  
Xor Gate ◽  
Xnor Gate ◽  
Gate Circuit ◽  
Field Programmable ◽  
New Research ◽  
Or Gate

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Holding replication studies to mainstream standards of evidence

2018 ◽  
Vol 41 ◽  
Author(s):  
Duane T. Wegener ◽  
Leandre R. Fabrigar
Keyword(s):  
Replication Studies ◽  
Replication Research ◽  
Standards Of Evidence ◽  
Do So

AbstractReplications can make theoretical contributions, but are unlikely to do so if their findings are open to multiple interpretations (especially violations of psychometric invariance). Thus, just as studies demonstrating novel effects are often expected to empirically evaluate competing explanations, replications should be held to similar standards. Unfortunately, this is rarely done, thereby undermining the value of replication research.

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