Titanium Oxide Memristor Based Digital Encoder Circuit

2014 ◽  
Vol 644-650 ◽  
pp. 3430-3433
Author(s):  
Yue Wei Hou ◽  
Xin Xu ◽  
Wei Wang ◽  
Xiao Bo Tian ◽  
Hai Jun Liu
Keyword(s):  
Titanium Oxide ◽  
Logic Gate ◽  
Logic Circuits ◽  
Practical Approach ◽  
Nand Gate ◽  
Gate Circuit

Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

Optical logic circuits using double controlled logic gate

2013 ◽  
Vol 7 (5) ◽  
pp. 99-109 ◽  
Author(s):  
Tanay Chattopadhyay
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Optical Logic

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Redox Active Binary Logic Gate Circuit for Homeland Security

2017 ◽  
Vol 89 (15) ◽  
pp. 7893-7899 ◽  
Author(s):  
Pramod Gaikwad ◽  
Kavita Kadlag ◽  
Manasa Nambiar ◽  
Mruthyunjayachari Chattanahalli Devendrachari ◽  
Shambhulinga Aralekallu ◽  
...  
Keyword(s):  
Homeland Security ◽  
Logic Gate ◽  
Binary Logic ◽  
Redox Active ◽  
Gate Circuit

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

N-channel field effect transistors with fullerene thin films and their application to a logic gate circuit

2003 ◽  
Vol 379 (3-4) ◽  
pp. 223-229 ◽  
Author(s):  
T. Kanbara ◽  
K. Shibata ◽  
S. Fujiki ◽  
Y. Kubozono ◽  
S. Kashino ◽  
...  
Keyword(s):  
Thin Films ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Gate ◽  
Gate Circuit

Logic Devices with Spin Wave Buses - an Approach to Scalable Magneto-Electric Circuitry

2008 ◽  
Vol 1067 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Yina Wu ◽  
Ji-Young Kim ◽  
Augustin Hong ◽  
...  
Keyword(s):  
Spin Wave ◽  
Room Temperature ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Logic Device ◽  
Logic Devices ◽  
Magnetic Circuits ◽  
Micrometer Scale ◽  
Magnetization Signal

ABSTRACTWe analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1μm2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

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