The Study on the Abrasion Characteristic of Wafer Surface According to Machining Condition

2009 ◽  
Vol 76-78 ◽  
pp. 381-386 ◽  
Author(s):  
Eun Sang Lee ◽  
Jong Koo Won ◽  
Jung Taik Lee ◽  
Hon Jong Choi

It is important to obtain the optimal condition in wafer polishing processing. Polishing is one of the most important methods in manufacturing of Si wafers and in thinning of completed device wafer. This study will report the evaluation on abrasion of wafer according to processing time; machining speed and pressure which have the major influence on the abrasion of Si wafer polishing, for this, this study design the head unit and analysis head unit. After that, this study applies to experiment. The evaluation of abrasion according to processing condition is selected to use result data that measure a pressure, machining speed, and the processing time. This result is appeared by machining condition. Through that, the study can evaluate the abrasion characteristic of wafer in machining.

2009 ◽  
Vol 626-627 ◽  
pp. 147-152
Author(s):  
Jong Koo Won ◽  
Jung Taik Lee ◽  
Eun Sang Lee

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafer. This study will report the evaluation on abrasion of wafer according to processing time; machining speed and pressure which have major influence on the abrasion of Si wafer polishing, for this, this study design the head unit and analysis head unit. After that, apply to experiment. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The evaluation of abrasion according to processing condition is selected to use result data that measure a pressure, machining speed, and the processing time. This result is appeared by abrasion in machining condition. Through that, the study cans evaluation a wafer abrasion in machining. It is important to obtain mirror-like wafer surface.


2008 ◽  
Vol 389-390 ◽  
pp. 493-497 ◽  
Author(s):  
Sung Chul Hwang ◽  
Jong Koo Won ◽  
Jung Taik Lee ◽  
Eun Sang Lee

As the level of Si-wafer surface directly affects device line-width capability, process latitude, yield, and throughput in fabrication of microchips, it needs to have ultra precision surface and flatness. Polishing is one of the important processing having influence on the surface roughness in manufacturing of Si-wafers. The surface roughness in wafer polishing is mainly affected by the many process parameters. For decreasing the surface roughness, the control of polishing parameters is very important. In this paper, the optimum condition selection of ultra precision wafer polishing and the effect of polishing parameters on the surface roughness were evaluated by the statistical analysis of the process parameters.


2012 ◽  
Vol 581-582 ◽  
pp. 790-793
Author(s):  
Xi Hui Zhang ◽  
Gui Xiang Wang

Several chelating agents in silicon polishing slurries were studied about their effects on copper adhesion to the surface of silicon wafer. The copper contamination level on the Si wafer surface was measured with GFAAS. The results indicate that PAA and HEDP for acid slurries can reduce 80% copper contamination with respect to the situation of without chelating agent. EDTA, the most common chelating agent for alkaline slurries, has no predominant compared with FA/O and AEEA. The copper contamination on Si wafer surface can reduce nearly 50% by adding EDTA while the addition of FA/O or AEEA in the same concentration for alkaline slurries can reach more than 70% reduction of copper contamination level.


2010 ◽  
Vol 126-128 ◽  
pp. 295-304
Author(s):  
Jung Taik Lee ◽  
Eun Sang Lee ◽  
Jong Koo Won ◽  
Hon Jong Choi

The polishing process of a silicon wafer is a critical factor in the fabrication of semiconductor. Because a globally planar and mirror-like wafer surface are achieved in this process. The surface roughness in the wafer depends on the surface properties of the carrier head unit along with other machining conditions such as working velocity, polishing pad, temperature, down-force, etc. In this paper, the wafer surface is investigated according to several parameters and experimental data. Experiments were performed to observe the down-force and temperature when the wafer carrier head unit was pressed down onto the polishing pad. A loadcell was employed to obtain the signal of the applied pressure against the polishing pad. Also, working temperature was detected using an infrared sensor. To study on the optimum conditions of machining, monitoring system is coded in Ch and the results of experiment present data using Ch.


2012 ◽  
Vol 497 ◽  
pp. 137-141 ◽  
Author(s):  
Wen Jian Lu ◽  
Yuki Shimizu ◽  
Wei Gao

A thermal-type contact sensor was proposed to detect small defects, the heights of which are less than 16 nm, on the wafer surface. The feasibility of the contact sensor, which detects frictional heat generated at the contact, was theoretically investigated focusing on the temperature rise of the sensor element. Simulation results with both the simple model of heat transfer and the FEM model showed that the expected temperature rise of the contact sensor is enough to be detected by the conventional electric circuit.


2006 ◽  
Vol 72 (11) ◽  
pp. 1363-1367
Author(s):  
Haruyuki INOUE ◽  
Toshihiko KATAOKA ◽  
Yoshihiro NAGAO ◽  
Yasushi OSHIKANE ◽  
Motohiro NAKANO ◽  
...  

1998 ◽  
Vol 65-66 ◽  
pp. 161-164 ◽  
Author(s):  
Osamu Nakamura ◽  
M. Yoshida ◽  
Yasuharu Shirai ◽  
Masakazu Nagase ◽  
Michio Kitano ◽  
...  

2003 ◽  
Vol 169-170 ◽  
pp. 178-180 ◽  
Author(s):  
S.H. Lee ◽  
J.G. Park ◽  
J.M. Lee ◽  
S.H. Cho ◽  
H.K. Cho

2007 ◽  
Vol 7 (11) ◽  
pp. 3792-3794 ◽  
Author(s):  
Ilsun Pang ◽  
Sungsoo Kim ◽  
Jaegab Lee

This study reports a novel patterning method for highly pure poly(3,4-ethylenedioxythiophene) (PEDOT) nanofilms having a particularly strong adhesion to a SiO2 surface. An oxidized silicon wafer substrate was micro-contact printed with n-octadecyltrichlorosilane (OTS) monolayer, and subsequently its negative pattern was self-assembled with three different amino-functionalized alkylsilanes, (3-aminopropyl)trimethoxysilane (APS), N-(2-aminoethyl)-3-aminopropyltrimethoxy silane (EDAS), and (3-trimethoxysilylpropyl) diethylenetriamine (DETS). Then, PEDOT nanofilms were selectively grown on the aminosilane pre-patterned areas via the vapor phase polymerization method. To evaluate the adhesion and patterning, the PEDOT nanofilms and SAMs were investigated with a Scotch® tape test, contact angle analyzer, optical and atomic force microscopes. The evaluation revealed that the newly developed bottom-up process can successfully offer a strongly adhered and selectively patterned PEDOT nanofilm on an oxidized Si wafer surface.


2011 ◽  
Vol 332-334 ◽  
pp. 1967-1973
Author(s):  
Yong Zhao ◽  
Xian Chen ◽  
Shuo Hou ◽  
Zai Kai Du ◽  
Guang Yang Mo ◽  
...  

Fe nano-films deposited on pure Si wafer by metal vapor vacuum arc (MEVVA) ion deposition system were annealed in hydrogen and then treated by ammonia at 750 °C for the catalyzed growth of aligned carbon nanotube (CNT) arrays. Influence of ammonia on the microstructures of Fe nano-films was analyzed by a field emission scanning electron microscopy (FESEM) and image analysis software. The microstructures of the post-processed Fe nano-films were found depending on the processing time of ammonia and the film thickness. Comparing the growth results of CNTs from 10 nm Fe films, we found that when the processing temperature was 750 °C, the optimum processing time of ammonia was about 10 to 12 min for 10 nm Fe films to catalyze the growth of aligned CNT arrays.


Sign in / Sign up

Export Citation Format

Share Document