Progress of RSFQ High Performance Packet Switch

2006 ◽  
Vol 47 ◽  
pp. 188-194
Author(s):  
Shinichi Yorozu ◽  
Yoshihito Hashimoto ◽  
Yoshio Kameda ◽  
Toshiyuki Miyazaki
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Semiconductor Technology ◽  
Switch Architecture ◽  
Traffic Loads ◽  
Rapid Single Flux Quantum ◽  
Switch System ◽  
Packet Switch ◽  
Switch Circuit

Internet traffic loads are increasing. Sustaining packet switching throughput of a core node will be difficult. A major reason for this is power consumption and packaging volume. As long as we use only current semiconductor technology, the switching capacity will be limited. Rapid single flux quantum (RSFQ) superconducting technology can overcome such difficulties because of high-speed operation and low-power consumption characteristics. A superconducting wiring also enables high-speed inter-chip communication. We report on progress on packet switch circuit implementation and cryo-cooled packaging for a RSFQ packet switch system. In addition, we discuss a possible packet switch architecture over 100 Tbps that uses RSFQ technology.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Energy-Aware Switch Design

2013 ◽  
pp. 341-360 ◽  
Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Single Chip ◽  
Energy Aware ◽  
It Industry ◽  
Gigabit Ethernet ◽  
Switch Architecture ◽  
Large Scale Integration ◽  
Scale Integration

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.

Low-power consumption seamless wireless and wired links using transparent waveform transfer

2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi
Keyword(s):  
Power Consumption ◽  
Optical Fiber ◽  
Low Power ◽  
Millimeter Wave ◽  
Optical Fibers ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

Sunshine: a high performance self-routing broadband packet switch architecture

1991 ◽  
Vol 9 (8) ◽  
pp. 1289-1298 ◽  
Author(s):  
J.N. Giacopelli ◽  
J.J. Hickey ◽  
W.S. Marcus ◽  
W.D. Sincoskie ◽  
M. Littlewood
Keyword(s):  
High Performance ◽  
Switch Architecture ◽  
Packet Switch

scholarly journals Variable rotor speed strategy for coaxial compound helicopters with lift–offset rotors

2019 ◽  
Vol 124 (1271) ◽  
pp. 96-120 ◽  
Author(s):  
Y. Yuan ◽  
D. Thomson ◽  
R. Chen
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Normal Load ◽  
Flight Dynamics ◽  
Load Factor ◽  
Rotor Speed ◽  
Inverse Simulation ◽  
Maneuvering Flight ◽  
The Impact

ABSTRACTThe coaxial compound helicopter with lift-offset rotors has been proposed as a concept for future high-performance rotorcraft. This helicopter usually utilizes a variable-speed rotor system to improve the high-speed performance and the cruise efficiency. A flight dynamics model of this helicopter associated with rotor speed governor/engine model is used in this article to investigate the effect of the rotor speed change and to study the variable rotor speed strategy. Firstly, the power-required results at various rotor rotational speeds are calculated. This comparison indicates that choice of rotor speed can reduce the power consumption, and the rotor speed has to be reduced in high-speed flight due to the compressibility effects at the blade tip region. Furthermore, the rotor speed strategy in trim is obtained by optimizing the power required. It is demonstrated that the variable rotor speed successfully improves the performance across the flight range, but especially in the mid-speed range, where the rotor speed strategy can reduce the overall power consumption by around 15%. To investigate the impact of the rotor speed strategy on the flight dynamics properties, the trim characteristics, the bandwidth and phase delay, and eigenvalues are investigated. It is shown that the reduction of the rotor speed alters the flight dynamics characteristics as it affects the stability, damping, and control power provided by the coaxial rotor. However, the handling qualities requirements are still satisfied with different rotor speed strategies. Finally, a rotor speed strategy associated with the collective pitch is designed for maneuvering flight considering the normal load factor. Inverse simulation is used to investigate this strategy on maneuverability in the Push-up & Pull-over Mission-Task-Element (MTE). It is shown that the helicopter can achieve Level 1 ratings with this rotor speed strategy. In addition, the rotor speed strategy could further reduce the power consumption and pilot workload during the maneuver.

The Application of Programmable Controller to Chip Design

2013 ◽  
Vol 273 ◽  
pp. 722-725
Author(s):  
Shi Hong Lan ◽  
Jian Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Automatic Control ◽  
High Performance ◽  
Low Power Consumption ◽  
System Software ◽  
Semiconductor Technology ◽  
Industrial Control ◽  
Chip Design ◽  
Chip Technology

In the field of modern industrial control, PLC has become the important equipment in automatic control. With the development of semiconductor technology, chip technology, the embedded PLC chipset emerged. The chipset microcontroller cores, PLC system software is loaded with high-performance, low power consumption, small size and other characteristics. User to flexibly customize according to their needs, using chipsets embedded PLC. This paper described the PLC chip design and application.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

scholarly journals Buried Powered 4t Sram with Improved Write Margin

2020 ◽  
Vol 9 (3) ◽  
pp. 2348-2351
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Sram Cell

The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology.

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