A Comparative Study of the Solder Joint Reliability in Flip Chip Assemblies with Compliant and Rigid Substrates

The reliability of solder joints in flip chip assemblies with both compliant (flex) and rigid (PCB) substrates was studied by accelerated temperature cycling tests and finite element modeling (FEM). In-process electrical resistance measurements and nondestructive evaluations were conducted to monitor solder joint failure behavior, hence the fatigue failure life. Meanwhile, the predicted fatigue failure life of solder joints was obtained by Darveaux’s crack initiation and growth models. It can be concluded that the solder joints in flip chip on flex assembly (FCOF) have longer fatigue life than those in flip chip on rigid board assembly (FCOB); the maximum von Mises stress/strain and the maximum shear stress/strain of FCOB solder joints are much higher than those of FCOF solder joints; the thermal strain and stress in solder joints is reduced by flex buckling or bending and flex substrate could dissipate energy that otherwise would be absorbed by solder joint. Therefore, the substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.

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Solder joint reliability modeling of 96.5Sn/3.5Ag flip chip bumps under temperature cycling condition

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003) ◽

10.1109/eptc.2003.1271498 ◽

2004 ◽

Cited By ~ 5

Author(s):

A. Yeo ◽

C. Lee ◽

J.H.L. Pang

Keyword(s):

Solder Joint ◽

Flip Chip ◽

Temperature Cycling ◽

Solder Joint Reliability ◽

Reliability Modeling ◽

Joint Reliability ◽

Cycling Condition

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Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology ◽

10.1115/imece2003-41993 ◽

2003 ◽

Cited By ~ 1

Author(s):

Guo-Quan Lu ◽

Xingsheng Liu ◽

Sihua Wen ◽

Jesus Noel Calata ◽

John G. Bai

Keyword(s):

Finite Element ◽

Solder Joint ◽

Thermal Cycling ◽

Flip Chip ◽

Solder Joints ◽

Mechanical Stresses ◽

Flexible Substrates ◽

Solder Joint Reliability ◽

Joint Reliability ◽

Reliability Of Solder Joints

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.

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Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

Microelectronics Reliability ◽

10.1016/j.microrel.2014.01.011 ◽

2014 ◽

Vol 54 (5) ◽

pp. 939-944 ◽

Cited By ~ 10

Author(s):

Ye Tian ◽

Xi Liu ◽

Justin Chow ◽

Yi Ping Wu ◽

Suresh K. Sitaraman

Keyword(s):

Solder Joint ◽

Experimental Evaluation ◽

Flip Chip ◽

Solder Joint Reliability ◽

Snagcu Solder ◽

Joint Reliability

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Evaluation of solder joint reliability in flip chip package under thermal shock test

Thin Solid Films ◽

10.1016/j.tsf.2005.09.097 ◽

2006 ◽

Vol 504 (1-2) ◽

pp. 426-430 ◽

Cited By ~ 15

Author(s):

Dae-Gon Kim ◽

Jong-Woong Kim ◽

Seung-Boo Jung

Keyword(s):

Solder Joint ◽

Thermal Shock ◽

Flip Chip ◽

Thermal Shock Test ◽

Solder Joint Reliability ◽

Shock Test ◽

Joint Reliability

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Solder Joint Reliability of SnBi Finished TSOPs with Alloy 42 Lead-Frame under Temperature Cycling

Lead-free Solders ◽

10.1520/stp49323s ◽

2011 ◽

pp. 74-74-15 ◽

Cited By ~ 1

Author(s):

Weiqiang Wang ◽

Michael Osterman ◽

Diganta Das ◽

Michael Pecht

Keyword(s):

Solder Joint ◽

Temperature Cycling ◽

Lead Frame ◽

Solder Joint Reliability ◽

Joint Reliability

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A Comparative Study of the Solder Joint Reliability in Flip Chip Assemblies with Compliant and Rigid Substrates

Key Engineering Materials - Progresses in Fracture and Strength of Materials and Structures ◽

10.4028/0-87849-456-1.2932 ◽

2007 ◽

pp. 2932-2935

Author(s):

Yong Chen Lin ◽

Xu Chen ◽

Xing Shen Liu ◽

Guo Quan Lu

Keyword(s):

Solder Joint ◽

Comparative Study ◽

Flip Chip ◽

Solder Joint Reliability ◽

Joint Reliability

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An improved peel stress-based correlation to predict solder joint reliability of lidded flip chip ball grid array packages

2015 IEEE 65th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2015.7159857 ◽

2015 ◽

Author(s):

Guangxu Li ◽

Siva P. Gurrum

Keyword(s):

Solder Joint ◽

Flip Chip ◽

Ball Grid Array ◽

Solder Joint Reliability ◽

Joint Reliability ◽

Ball Grid Array Packages ◽

Peel Stress

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FCBGA Footprints and Solder Joint Reliability

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2004-60041 ◽

2004 ◽

Author(s):

Frank Z. Liang ◽

Rick L. Williams

Keyword(s):

Solder Joint ◽

Flip Chip ◽

Electrical Performance ◽

Solder Joint Reliability ◽

Routing Optimization ◽

Joint Reliability ◽

Cost Constraints ◽

Package Size ◽

Empirical Tests ◽

The One

As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer’s critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models.

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