Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

2011 ◽  
Vol 483 ◽  
pp. 38-42 ◽  
Author(s):  
Le Guan ◽  
Jia Li Gao ◽  
Jin Kui Chu
Keyword(s):  
Krylov Subspace ◽  
Test System ◽  
Differential Capacitance ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Electrothermal Actuator ◽  
System Level Simulation ◽  
Circuit Components ◽  
On Chip

The methods of on-chip integrated testing have a wide application with the development of the study for MEMS materials properties measurement in microscale. A novel on-chip integrated micro-tensile testing system is designed through system-level simulation based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The structure of testing instrument consists of V-beam electrothermal actuator, differential capacitance sensor, supporting spring and specimen. The capacitance signal is sensed and controlled by a second sigma-delta modulator circuit. The analytic macromodel of polysilicon thin film specimen considering geometric nonlinearity and the numerical reduced-order model of V-beam electrothermal actuator based on Krylov subspace projection are created separately and described in the MAST hardware language. The mechanical structure dimension size and circuit components parameters are determined and optimized according to system-level simulation. The computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable.

A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors

2013 ◽  
Vol 562-565 ◽  
pp. 311-316
Author(s):  
Xiao Wei Liu ◽  
Qiang Li ◽  
Guan Nan Sun ◽  
Wen Yan Liu
Keyword(s):  
Inertial Sensors ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Technical Requirements ◽  
System Level Simulation ◽  
Multi Stage ◽  
Multi Phase

The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films

2013 ◽  
Vol 562-565 ◽  
pp. 930-934
Author(s):  
Le Guan ◽  
Jia Li Gao ◽  
Qi Liu ◽  
Bin Li ◽  
Jin Kui Chu
Keyword(s):  
Simulation Method ◽  
Test System ◽  
Test Structure ◽  
System Level ◽  
Bending Test ◽  
Static And Dynamic Analysis ◽  
System Level Simulation ◽  
Parts Library ◽  
Peking University ◽  
On Chip

Two kind of on-chip integrated fatigue bending test structures are designed through system-level simulation method based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The first on-chip fatigue test structure is actuated by V-beam thermal actuator, and the other test structure actuated by electrostatic comb. The static and dynamic analysis was performed by Coventorware Architect module using self-bulid reduced order model described with the MAST hardware language and some other commercial parts from Coventorware parts library. The structural dimension parameters are determined and optimized according to system-level simulation and the computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable. Two kinds of polysilicon on-chip fatigue bending test structure were fabricated with two-layer polysilicon surface micromachining process in Institute of Microelectronics, Peking University.

A High-Performance Mash Fourth-Order Sigma-Delta Modulator

2012 ◽  
Vol 503 ◽  
pp. 207-210
Author(s):  
Wen Yan Liu ◽  
Bin Zhang ◽  
Long Chen ◽  
Chao Gao ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
System Stability ◽  
Quantization Noise ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
System Level Simulation ◽  
Sampling Ratio ◽  
Σδ Modulator

This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.

On-Chip Touch Sensor Readout Circuit Using Passive Sigma-Delta Modulator Capacitance-to-Digital Converter

2015 ◽  
Vol 15 (7) ◽  
pp. 3893-3902 ◽  
Author(s):  
Bo Liu ◽  
Zaniar Hoseini ◽  
Kye-Shin Lee ◽  
Yong-Min Lee
Keyword(s):  
Readout Circuit ◽  
Digital Converter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Touch Sensor ◽  
On Chip

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

scholarly journals Ferrimagnetic Synapse Devices for Fast and Energy-Efficient On-Chip Learning on An Analog-Hardware Neural Network

2021 ◽  
Author(s):  
Upasana Sahu ◽  
Naven Sisodia ◽  
Janak Sharda ◽  
Pranaba Kishor Muduli ◽  
Debanjan Bhowmik
Keyword(s):  
Domain Wall ◽  
Energy Efficient ◽  
Velocity Ratio ◽  
Domain Wall Motion ◽  
System Level ◽  
System Level Simulation ◽  
On Chip ◽  
Experimental Findings ◽  
Fully Connected ◽  
Hardware Neural Network

we have modeled domain-wall motion in ferrimagnetic and ferromagnetic devices through micro magnetics and shown that the domain-wall velocity can be 2–2.5X faster in the ferrimagnetic device compared to the ferromagnetic device. We also show that this velocity ratio is consistent with recent experimental findings Because of such a velocity ratio, when such devices are used as synapses in the crossbar-array-based fully connected network, our system-level simulation here shows that a ferrimagnet-synapse-based crossbar offers 4X faster (for the same energy efficiency) or 4X more energy-efficient (for the same speed) learning when compared to the ferromagnet-synapse-based crossbar.

A High Performance Fourth-Order Single-Loop Sigma Delta Modulator Applied in Micro-Inertial Sensors

2012 ◽  
Vol 503 ◽  
pp. 303-307
Author(s):  
Peng Fei Wang ◽  
Yuan Yuan ◽  
Dong Bo Wang ◽  
Xiao Wei Liu ◽  
Jun'an Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
Inertial Sensors ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analysis And Design ◽  
The Stability ◽  
Σδ Modulator

This paper presents a fourth-order sigma delta (ΣΔ)modulator applied in micro-inertial sensors. After a introduction of sigma-delta modulator and its application in micro-inertial sensors, the system-level analysis and design is given and the gain coefficients is calculated. By the use of root locus, the stability of high order ΣΔ modulator is analyzed and it is got the minimum value of quantizer gain k is 0.287. The simulation shows that the signal to noise ratio (SNR) is 121.6 dB and the effective number of bits (ENOB) is 19.91 bits. When input level is smaller than -6 dBFs, the quantizer and integrators would not be overload and work well.

scholarly journals Ferrimagnetic Synapse Devices for Fast and Energy-Efficient On-Chip Learning on An Analog-Hardware Neural Network

2021 ◽  
Author(s):  
Upasana Sahu ◽  
Naven Sisodia ◽  
Janak Sharda ◽  
Pranaba Kishor Muduli ◽  
Debanjan Bhowmik
Keyword(s):  
Domain Wall ◽  
Energy Efficient ◽  
Velocity Ratio ◽  
Domain Wall Motion ◽  
System Level ◽  
System Level Simulation ◽  
On Chip ◽  
Experimental Findings ◽  
Fully Connected ◽  
Hardware Neural Network

we have modeled domain-wall motion in ferrimagnetic and ferromagnetic devices through micro magnetics and shown that the domain-wall velocity can be 2–2.5X faster in the ferrimagnetic device compared to the ferromagnetic device. We also show that this velocity ratio is consistent with recent experimental findings Because of such a velocity ratio, when such devices are used as synapses in the crossbar-array-based fully connected network, our system-level simulation here shows that a ferrimagnet-synapse-based crossbar offers 4X faster (for the same energy efficiency) or 4X more energy-efficient (for the same speed) learning when compared to the ferromagnet-synapse-based crossbar.

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