Stress Test of Cascode Switch Using SiC Static Induction Transistor

2020 ◽  
Vol 1004 ◽  
pp. 985-991
Author(s):  
Takashi Matsumoto ◽  
Yasunori Tanaka ◽  
Koji Yano
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Drain Current ◽  
Electrical Characteristics ◽  
Stress Tests ◽  
Turn On ◽  
Significant Difference ◽  
Static Induction Transistor ◽  
Static Induction ◽  
Channel Region

Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

Radiation Hardness of 4H-SiC JFETs in MGy Dose Ranges

2020 ◽  
Vol 1004 ◽  
pp. 1109-1114
Author(s):  
Akinori Takeyama ◽  
Keigo Shimizu ◽  
Takahiro Makino ◽  
Yuichi Yamazaki ◽  
Shin Ichiro Kuroki ◽  
...  
Keyword(s):  
Gamma Rays ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Leakage Currents ◽  
Transfer Characteristics ◽  
Pristine Sample ◽  
Significant Difference ◽  
Apparent Shift ◽  
Channel Region

Silicon carbide junction field effect transistors (SiC JFETs) were irradiated with gamma-rays up to 9 MGy (H2O). With increasing dose, apparent shift of drain current-gate voltage (ID-VG) curves to negative voltage side as observed for SiC metal oxide semiconductor (MOS) FETs did not take place. No significant difference is observed between drain and gate leakage currents of irradiated JFETs. This strongly indicates that defects as leakage paths were introduced into not bulk region but the interface between bulk and the passivation layer of SiO2. While, the transfer characteristics including threshold voltage and transconductance were slightly changed compared with the pristine sample. After drain voltage (VD) was abruptly applied to 6 V, ID at VG= 0 V increased slowly as a function of time. This indicates that variation of transfer characteristics is attributed to capture and emission process at defects generated in channel region.

1270V, 1.21mΩ·cm2 SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

2008 ◽  
Vol 600-603 ◽  
pp. 1071-1074 ◽  
Author(s):  
Yasunori Tanaka ◽  
Koji Yano ◽  
Mitsuo Okamoto ◽  
Akio Takatsuka ◽  
Kazuo Arai ◽  
...  
Keyword(s):  
Time Delay ◽  
The Other ◽  
Gate Electrodes ◽  
Turn On ◽  
Static Induction Transistors ◽  
Operation Temperature ◽  
Barrier Formation ◽  
Static Induction ◽  
The Difference ◽  
Channel Region

We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.

Investigation of Forward Voltage Degradation due to Process-Induced Defects in 4H-SiC MOSFET

2018 ◽  
Vol 924 ◽  
pp. 365-368 ◽  
Author(s):  
Kumiko Konishi ◽  
Ryusei Fujita ◽  
Yuki Mori ◽  
Akio Shima
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Implantation Dose ◽  
Imaging Method ◽  
Stress Tests ◽  
Forward Voltage ◽  
Current Stress ◽  
Before And After ◽  
Induced Defects ◽  
Voltage Degradation

We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

Electrical Characteristics of a Novel Gate Structure 4H-SiC Power Static Induction Transistor

1998 ◽  
Vol 264-268 ◽  
pp. 1085-1088 ◽  
Author(s):  
T. Iwasaki ◽  
T. Oono ◽  
Katsunori Asano ◽  
Yoshitaka Sugawara ◽  
Tsutomu Yatsuo
Keyword(s):  
Electrical Characteristics ◽  
Gate Structure ◽  
Static Induction Transistor ◽  
Static Induction

Probing Drain Current with Vertical and Horizontal Electrical Fields under Temperature Stress on CLC TFTs

2011 ◽  
Vol 314-316 ◽  
pp. 1922-1925 ◽  
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang
Keyword(s):  
Electric Fields ◽  
Thin Film Transistors ◽  
Continuous Wave ◽  
Drain Current ◽  
Green Laser ◽  
Electrical Characteristics ◽  
Effective Electron ◽  
Electrical Fields ◽  
Single Grain ◽  
Channel Region

Thin-film transistors (TFT) usually exhibit non-uniform electrical characteristics fabricated by the identical process because of the formation of the grain boundary traps, bulk grain traps, interface states and some defects on channel region. All the traps and defects affecting the electrical characteristics of TFTs can be thermally and electrically activated. In this study, the temperature effect accompanying the horizontal and vertical electric fields stressing on continuous-wave green laser-crystallized (CLC) single-grain-like poly silicon TFTs (poly-Si TFTs), presenting the excellent effective electron mobility, up to 530 cm^2/V-s, was firstly investigated.

scholarly journals IMPROVED PROCESS FLOW FOR FORMATION OF BIPOLAR STATIC INDUCTION TRANSISTOR

2018 ◽  
Vol 17 (1) ◽  
pp. 72-78 ◽  
Author(s):  
N. L. Lagunovich
Keyword(s):  
Process Simulation ◽  
Electrical Characteristics ◽  
Semiconductor Wafer ◽  
Process Flow ◽  
Software Products ◽  
Virtual Production ◽  
Current Voltage ◽  
Static Induction Transistor ◽  
Current Voltage Characteristics ◽  
Static Induction

The improved process flow differs from the known ones in the fact that the same photomask is used for formation of a channel stopper and metal contacts. Such approach has made it possible not only to decrease a number of the used phototomasks but it has also permitted to obtain a device with the required electrical characteristics. The paper presnts results of device and process simulation of bipolar static induction transistor (BSIT) manufactured in accordance with the improved process flow, measuring data of electrophysical parameters of its experimental samples and also comparison of simulation results with experimental data. At present there is a large quantity of software products that permit to perform physico-topological simulation of semiconductor structures. The device-process simulation is considered as a part of such simulation and it allows prior to obtaining experimental samples to determine process flow parameters at which the investigated structure will have necessary electrical parameters and characteristics. Thus the device-process simulation represents a certain “virtual production” for manufacturing semiconductor devices and microcircuits beginning from the startup stage of semiconductor wafer at production site and finishing by electrical characteristics measurements of the obtained structure. The BSIT device simulation being an analog of direct measurements of current-voltage characteristics has been performed with help of program system MOD-1D developed by the author. The BSIT model based on the fundamental system of semiconductor equations is mainly used for calculation of the BSIT current-voltage characteristics direct branch and its parameters and charge carrier recombination is described by Shockley – Read – Hall expression and equation depicting the Auger recombination process.

scholarly journals Quality of One-channel Telemetric ECG Sensor Signal in Maximum Exercise Stress Tests

2019 ◽  
Vol 19 (3) ◽  
pp. 79-85 ◽  
Author(s):  
Boris Širaiy ◽  
Roman Trobec ◽  
Vladimir Ilić
Keyword(s):  
Stress Test ◽  
Cycle Ergometer ◽  
The Body ◽  
Exercise Stress ◽  
Ecg Signal ◽  
Stress Tests ◽  
Concurrent Use ◽  
Significant Difference ◽  
Sensor Positions

Abstract The aim of this study was to evaluate the quality of the ECG signal, obtained from a telemetric body-sensor device during a maximum stress test on an ergometer. Twenty-three subjects, 13 males, were included in the study (20.56±1.19 years). Two different sensor positions were verified on each subject by the concurrent use of two ECG sensors. Each subject participated in four exercise stress tests: two on a treadmill and two on a cycle ergometer. In the first test, both sensors were attached to self-adhesive skin electrodes on the body, while in the second test the sensors were additionally fixed with self-adhesive tapes. The measurements were compared on both ergometers, in terms of the ECG sensors’ positions and the methods used for the sensors’ fixation. The results showed a significant difference in the running speed that provides an assessable ECG signal between the non-fixed and the fixed sensors at position left inferior (p = 0.000), as well as between the positions left inferior and left superior in the first (p = 0.019), and in the second test (p = 0.000) on the treadmill. On the cycle ergometer the differences were significant between the positions left inferior and left superior in the first (p = 0.000), and the second test (p = 0.003), and between the tests with fixed and non-fixed sensors in the position left superior (p = 0.011). The study confirms that ECG sensors could be used for maximal exercise stress tests in laboratories, especially on a cycle ergometer, and that they present a great potential for future use of ECG sensors during physical activity.

Sign in / Sign up

Export Citation Format

Share Document