RF Characteristics of a Fully Ion-Implanted MESFET with Highly Doped Thin Channel Layer on a Bulk Semi-Insulating 4H-SiC Substrate.

2008 ◽  
Vol 600-603 ◽  
pp. 1107-1110 ◽  
Author(s):  
S. Katakami ◽  
Shuichi Ono ◽  
Manabu Arai
Keyword(s):  
Ion Implantation ◽  
Output Power ◽  
Electrical Characteristics ◽  
Device Design ◽  
Channel Layer ◽  
Thin Channel ◽  
Saturated Output Power ◽  
Recessed Gate ◽  
Better Than ◽  
Ion Implanted

We fabricated a 0.5-μm-gate MESFET on a bulk 4H-SiC semi-insulating substrate using ion implantation for the channel and contact regions. Our device design used a thin, highly doped channel layer, which was implanted at single energy to improve the device’s RF characteristics. The electrical characteristics of the ion-implanted MESFET annealed at 1700°C were better than those of the ion-implanted MESFET annealed at 1300°C. The fabricated ion-implanted MESFET has a maximum transconductance of 32.8 mS/mm and an fT/fmax of 9.1/26.2 GHz. The saturated output power was 26.2 dBm (2.1 W/mm) at 2 GHz. These values were the same as those of the conventional epitaxial MESFET with a recessed gate.

Improvement of Electrical Characteristics of Ion Implanted 4H-SiC MESFET on a Semi-Insulating Substrate

2007 ◽  
Vol 556-557 ◽  
pp. 803-806 ◽  
Author(s):  
S. Katakami ◽  
Makoto Ogata ◽  
Shuichi Ono ◽  
Manabu Arai
Keyword(s):  
Ion Implantation ◽  
Epitaxial Growth ◽  
Channel Structure ◽  
Doping Profile ◽  
Implantation Technique ◽  
Electrical Characteristics ◽  
Structure Characteristics ◽  
Channel Layer ◽  
One Step ◽  
Ion Implanted

The electrical characteristics of a SiC-MESFET are affected by the channel structure characteristics, such as impurity density and thickness. MESFETs fabricated with ion implantation technique, can form thinner and higher doped channel layers than those fabricated with conventional epitaxial growth, thus improve RF characteristics of MESFETs. We calculated the doping profile of the channel layer for an ion implanted SiC-MESFET using a simulator and then fabricated a SiC-MESFET with the same doping profile as obtained from the simulation. The ion implanted SiC-MESFET operated successfully and had the same electrical characteristics as the epitaxial SiC-MESFET. We demonstrated the effectiveness of one-step implantation channel layer for the ion implanted SiC-MESFET.

Ion Implantation Defects in 4H-SiC DIMOSFET

2016 ◽  
Vol 858 ◽  
pp. 418-421 ◽  
Author(s):  
Enzo Fontana ◽  
Nicolò Piluso ◽  
Alfio Russo ◽  
Simona Lorenti ◽  
Cinzia M. Marcellino ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Point Defects ◽  
Electrical Characteristic ◽  
Source Region ◽  
Considerable Improvement ◽  
Large Reduction ◽  
Electrical Characteristics ◽  
Implantation Process ◽  
Ion Implanted

In this paper the influence of point defects generated by the ion implantation process in 4H-SiC DIMOSFET has been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. In particular it has been observed that a reduction of the source ion implanted dose produces a large reduction of point defects in the source region and a considerable improvement of the electrical characteristic of the DIMOSFET.

Electron Diffraction Analysis of Microtwin Structures in Regrown (III) Silicon

1982 ◽  
Vol 40 ◽  
pp. 460-461
Author(s):  
P. Ling ◽  
R. Gronsky ◽  
J. Washburn
Keyword(s):  
Electron Diffraction ◽  
Ion Implantation ◽  
Diffraction Analysis ◽  
Diffraction Pattern ◽  
Direct Consequence ◽  
The Other ◽  
Electron Diffraction Analysis ◽  
Defect Microstructures ◽  
Ion Implanted

The defect microstructures of Si arising from ion implantation and subsequent regrowth for a (111) substrate have been found to be dominated by microtwins. Figure 1(a) is a typical diffraction pattern of annealed ion-implanted (111) Si showing two groups of extra diffraction spots; one at positions (m, n integers), the other at adjacent positions between <000> and <220>. The object of the present paper is to show that these extra reflections are a direct consequence of the microtwins in the material.

Switching the electrical characteristics of TiO2 from n-type to p-type by ion implantation

2021 ◽  
pp. 150274
Author(s):  
Adriano Panepinto ◽  
Arnaud Krumpmann ◽  
David Cornil ◽  
Jérôme Cornil ◽  
Rony Snyders
Keyword(s):  
Ion Implantation ◽  
Electrical Characteristics ◽  
P Type

Scanned Electron Beam Annealing of Boron-Implanted Diodes

1980 ◽  
Vol 1 ◽  
Author(s):  
T. O. Yep ◽  
R. T. Fulks ◽  
R. A. Powell
Keyword(s):  
Electron Beam ◽  
Ion Implantation ◽  
Reverse Bias ◽  
Carrier Lifetime ◽  
Reverse Current ◽  
Electrical Activation ◽  
Electrical Characteristics ◽  
Low Resolution ◽  
Implantation Damage ◽  
Dopant Redistribution

ABSTRACTSuccessful annealing of p+ n arrays fabricated by ion-implantation of 11B (50 keV, 1 × 1014 cm-2) into Si (100 has been performed using a broadly rastered, low-resolution (0.25-inch diameter) electron beam. A complete 2" wafer could be uniformly annealed in ≃20 sec with high electrical activation (>75%) and small dopant redistribution (≃450 Å). Annealing resulted In p+n junctions characterized by low reverse current (≃4 nAcm-2 at 5V reverse bias) and higher carrier lifetime (80 μsec) over the entire 2" wafer. Based on the electrical characteristics of the diodes, we estimate that the electron beam anneal was able to remove ion implantation damage and leave an ordered substrate to a depth of 5.5 m below the layer junction.

Optimization of InP DHBT stacked-transistors for millimeter-wave power amplifiers

2018 ◽  
Vol 10 (9) ◽  
pp. 999-1010 ◽  
Author(s):  
Michele Squartecchia ◽  
Tom K. Johansen ◽  
Jean-Yves Dupuy ◽  
Virginio Midili ◽  
Virginie Nodjiadjim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Output Power ◽  
Heterojunction Bipolar Transistors ◽  
Power Amplifiers ◽  
Small Signal Gain ◽  
Small Signal ◽  
Large Signal ◽  
Signal Gain ◽  
Power Added Efficiency ◽  
Saturated Output Power

AbstractIn this paper, we report the analysis, design, and implementation of stacked transistors for power amplifiers realized on InP Double Heterojunction Bipolar Transistors (DHBTs) technology. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations. An evaluation of the maximum number of transistors for positive incremental power and gain is also carried out. To validate the analysis, E-band three- and four-stacked InP DHBT matched power cells have been realized for the first time as monolithic microwave integrated circuits (MMICs). For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm, and a peak power added efficiency (PAE) of 5.2% have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8%. A four-way combined three-stacked MMIC power amplifier has been implemented as well. It exhibits a linear gain of 8.1 dB, a saturated output power higher than 18 dBm, and a PAE higher than 3% at 84 GHz.

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

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