Circuit Modeling of Vertical Buried-Grid SiC JFETs

2010 ◽  
Vol 645-648 ◽  
pp. 965-968
Author(s):  
Georg Tolstoy ◽  
Dimosthenis Peftitsis ◽  
Jang Kwon Lim ◽  
Mietek Bakowski ◽  
Hans Peter Nee
Keyword(s):  
Threshold Voltage ◽  
Circuit Model ◽  
Circuit Modeling ◽  
Short Channel ◽  
Simulation Data ◽  
New Model ◽  
Source Voltage

The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Equivalent Circuit Modeling of a Dual-Gate Graphene FET

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 63
Author(s):  
Saima Hasan ◽  
Abbas Z. Kouzani ◽  
M A Parvez Mahmud
Keyword(s):  
Equivalent Circuit ◽  
Gate Voltage ◽  
Voltage Dependence ◽  
Drain Current ◽  
Bilayer Graphene ◽  
Circuit Modeling ◽  
Equivalent Circuit Modeling ◽  
Dual Gate ◽  
Source Voltage ◽  
Transit Frequency

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.

scholarly journals Generation of elementary gates and Bell’s states using controlled adiabatic evolutions

2019 ◽  
Vol 17 (03) ◽  
pp. 1950020
Author(s):  
Abderrahim Benmachiche ◽  
Ali Sellami ◽  
Sherzod Turaev ◽  
Derradji Bahloul ◽  
Azeddine Messikh ◽  
...  
Keyword(s):  
Quantum Computation ◽  
Open Systems ◽  
Circuit Model ◽  
Quantum Gates ◽  
Single Quantum ◽  
New Model ◽  
Adiabatic Quantum Computation ◽  
Usual Quantum

Fundamental quantum gates can be implemented effectively using adiabatic quantum computation or circuit model. Recently, Hen combined the two approaches to introduce a new model called controlled adiabatic evolutions [I. Hen, Phys. Rev. A, 91(2) (2015) 022309]. This model was specifically designed to implement one and two-qubit controlled gates. Later, Santos extended Hen’s work to implement [Formula: see text]-qubit controlled gates [A. C. Santos and M. S. Sarandy, Sci. Rep., 5 (2015) 15775]. In this paper, we discuss the implementation of each of the usual quantum gates, as well as demonstrate the possibility of preparing Bell’s states using the controlled adiabatic evolutions approach. We conclude by presenting the fidelity results of implementing single quantum gates and Bell’s states in open systems.

An analytical model for anomalous threshold voltage behavior of short channel MOSFETs

1997 ◽  
Vol 41 (9) ◽  
pp. 1386-1388 ◽  
Author(s):  
Manoj K. Khanna ◽  
Maneesha ◽  
Ciby Thomas ◽  
R.S. Gupta ◽  
Subhasis Haldar
Keyword(s):  
Analytical Model ◽  
Threshold Voltage ◽  
Short Channel ◽  
Anomalous Threshold

The impact of channel-width on threshold voltage for short channel devices

2011 ◽  
Author(s):  
Kiran Agarwal Gupta ◽  
V Venkateswarlu ◽  
Dinesh Anvekar ◽  
Sumit Basu
Keyword(s):  
Threshold Voltage ◽  
Channel Width ◽  
Short Channel ◽  
The Impact

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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