Demonstration of SiC Vertical Trench JFET Reliability

2012 ◽  
Vol 717-720 ◽  
pp. 1017-1020 ◽  
Author(s):  
Kevin M. Speer ◽  
Kiran Chatty ◽  
Volodymyr Bondarenko ◽  
David C. Sheridan ◽  
Kevin Matocha ◽  
...  
Keyword(s):  
High Temperature ◽  
Circuit Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Measured Parameter ◽  
System Operation ◽  
Dislocation Glide ◽  
Temperature Bias ◽  
Bias Stress

This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

SiC Field Effect Transistor Technology Demonstrating Prolonged Stable Operation at 500 °C

2007 ◽  
Vol 556-557 ◽  
pp. 831-834 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Liang Yu Chen ◽  
Robert S. Okojie ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
High Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Degradation Mechanism ◽  
Low Frequency ◽  
Common Source ◽  
Stable Operation ◽  
Air Atmosphere ◽  
Voltage Amplifier

While there have been numerous reports of short-term transistor operation at 500 °C or above, these devices have previously not demonstrated sufficient long-term operational durability at 500 °C to be considered viable for most envisioned applications. This paper reports the development of SiC field effect transistors capable of long-term electrical operation at 500 °C. A 6H-SiC MESFET was packaged and subjected to continuous electrical operation while residing in a 500 °C oven in oxidizing air atmosphere for over 2400 hours. The transistor gain, saturation current (IDSS), and on-resistance (RDS) changed by less than 20% from initial values throughout the duration of the biased 500 °C test. Another high-temperature packaged 6H-SiC MESFET was employed to form a simple one-stage high-temperature low-frequency voltage amplifier. This single-stage common-source amplifier demonstrated stable continuous electrical operation (negligible changes to gain and operating biases) for over 600 hours while residing in a 500 °C air ambient oven. In both cases, increased leakage from annealing of the Schottky gate-to-channel diode was the dominant transistor degradation mechanism that limited the duration of 500 °C electrical operation.

scholarly journals Bias stress effect in polyelectrolyte-gated organic field-effect transistors

2013 ◽  
Vol 102 (11) ◽  
pp. 113306 ◽  
Author(s):  
H. Sinno ◽  
S. Fabiano ◽  
X. Crispin ◽  
M. Berggren ◽  
I. Engquist
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Stress Effect ◽  
Organic Field Effect Transistors ◽  
Bias Stress

High-temperature modeling and characterization of 6H silicon carbide metal-oxide-semiconductor field-effect transistors

2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Temperature Modeling

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

Influence of High-Temperature Bias Stress on Room-Temperature VT Drift Measurements in SiC Power MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 757-762
Author(s):  
Daniel B. Habersat ◽  
Aivars Lelis ◽  
Ronald Green
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
State Of The Art ◽  
Charge Trapping ◽  
High Temperature Stress ◽  
Test Method ◽  
Power Mosfets ◽  
Temperature Bias ◽  
Bias Stress

Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for VT stability.

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