Fabrication and Characterization of 3.3-kV SiC DMOSFET with Self-Aligned Channels Formed by Tilted Ion Implantation

2019 ◽  
Vol 963 ◽  
pp. 390-393
Author(s):  
Takahiro Morikawa ◽  
Shintaroh Sato ◽  
Akio Shima
Keyword(s):  
Ion Implantation ◽  
Threshold Voltage ◽  
Experimental Results ◽  
Channel Formation ◽  
Electrical Measurements ◽  
Blocking Voltage ◽  
Fabrication And Characterization ◽  
State Resistance

SiC DMOSFET with self-aligned channels was fabricated and characterized. The process features self-aligned channel formation by utilizing tilted ion implantation. We confirmed that channel areas were successfully formed along both sides of the stripe cell. Electrical measurements revealed that the characteristics of the fabricated DMOSFET chips had sufficiently high blocking voltage and moderate values of threshold voltage and on-state resistance. These experimental results show the proposed process can be an easy option for fabrication of SiC DMOSFET.

Fabrication and Characterization of 4H-SiC 6kV Gate Turn-Off Thyristor

2012 ◽  
Vol 717-720 ◽  
pp. 1163-1166 ◽  
Author(s):  
Lei Lin ◽  
Jian Hui Zhao
Keyword(s):  
High Current Density ◽  
High Current ◽  
Initial Pulse ◽  
Large Area ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Pulse Testing ◽  
Blocking Voltage ◽  
Fabrication And Characterization

In this paper, we report a 0.1cm2 4H-SiC gate-turn-off (GTO) thyristor with 6 kV blocking voltage fabricated on a structure with a 60µm blocking layer. A relatively large area, high voltage 4H-SiC GTO that exhibits encouraging characteristic at the on- and off-states, and a low leakage current with 63% devices blocking 3kV or higher. Initial pulse testing result shows that the fabricated GTOs are capable of both high current density and high turn-off speed.

Fabrication and Characterization of Cr-Based Schottky Diode on n-Type 4H-SiC

2009 ◽  
Vol 615-617 ◽  
pp. 651-654 ◽  
Author(s):  
C. Koliakoudakis ◽  
J. Dontas ◽  
S. Karakalos ◽  
M. Kayambaki ◽  
S. Ladas ◽  
...  
Keyword(s):  
Barrier Height ◽  
Schottky Diode ◽  
Photoelectron Spectroscopy ◽  
Schottky Contacts ◽  
Electrical Measurements ◽  
A Value ◽  
Fabrication And Characterization

The behavior of 200nm Cr Schottky contacts on n-type 4H-SiC has been investigated with photoelectron spectroscopy (XPS) and standard (I-V and C-V) electrical measurements at different measurement temperatures. A barrier height close to 1.2 eV was calculated from XPS data under no-current and no-bias conditions on ultra-thin Cr films grown in-situ under UHV conditions. The I-V measurements on as-deposited contacts resulted in a barrier height of 1.06 eV while a value of 1.2 eV has been extracted from the C-V measurements.

scholarly journals Fabrication and characterization of a co-planar detector in diamond for low energy single ion implantation

2016 ◽  
Vol 109 (6) ◽  
pp. 063502 ◽  
Author(s):  
J. B. S. Abraham ◽  
B. A. Aguirre ◽  
J. L. Pacheco ◽  
G. Vizkelethy ◽  
E. Bielejec
Keyword(s):  
Ion Implantation ◽  
Low Energy ◽  
Planar Detector ◽  
Fabrication And Characterization

Measurement Issues Affecting Threshold-Voltage Instability Characterization of SiC MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 461-464 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Bias ◽  
Electrical Measurements ◽  
Power Mosfets ◽  
Measurement Issues ◽  
Bias Stress ◽  
Bias Temperature Instability ◽  
Yield Test

This work focuses on measurement issues that affect the accuracy of positive bias temperature instability measurements of SiC power MOSFETs using a conventional sweep technique to characterize the threshold voltage, VT. Threshold-voltage shifts occurring during stress are readily recoverable during the measurement, resulting in an underestimation in VT degradation. Recovery of VT due to gate-stress relaxation before or during the measurement was a major source of measurement error that was mitigated by performing an immediate sweep down in gate voltage, VGS, from the stress bias toward threshold. Allowing the gate bias to drop to zero just prior to measuring by sweeping VGS positively resulted in smaller observed degradation due to VT recovery. This result is important, especially in cases where the gate stress has to be completely removed before making any electrical measurements. The VT shift caused by bias stress can quickly recover and yield test results that underestimate the effect of the applied stress. A full recovery of VT was observed following a positive gate bias stress for conditions where the gate was either subject to a negative gate voltage for a few seconds, or when VGS was maintained at zero volts for several minutes.

Fabrication and Characterization of 4H-SiC Planar MESFET Using Ion- Implantation

2004 ◽  
Vol 457-460 ◽  
pp. 1181-1184 ◽  
Author(s):  
Hoon Joo Na ◽  
Dae Hwan Kim ◽  
Sang Yong Jung ◽  
In Bok Song ◽  
Myung Yoon Um ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Fabrication And Characterization

Fabrication and characterization of Ge nanocrystalline growth by ion implantation in SiO2 matrix

2007 ◽  
Vol 42 (18) ◽  
pp. 7757-7761 ◽  
Author(s):  
S. N. M. Mestanza ◽  
I. Doi ◽  
J. W. Swart ◽  
N. C. Frateschi
Keyword(s):  
Ion Implantation ◽  
Sio2 Matrix ◽  
Fabrication And Characterization

Design, Fabrication and Characterization of a 4.5kV / 50A 4H-SiC PiN Rectifiers

2019 ◽  
Vol 954 ◽  
pp. 85-89
Author(s):  
Yue Wei Liu ◽  
Rui Xia Yang ◽  
Xiao Chuan Deng
Keyword(s):  
High Power ◽  
Room Temperature ◽  
Parallel Plane ◽  
Electrical Performance ◽  
Optimum Process ◽  
Forward Current ◽  
Blocking Voltage ◽  
Fabrication And Characterization ◽  
Numerical Device

In this work, a 4.5kV/50A 4H-SiC PiN rectifiers with mesa combined with double-JTE structures is successfully developed for high power applications. Two-dimension numerical device simulator Silvaco-TCAD is applied to optimizing the electrical performance of fabricated rectifiers. Mesa-combined double-JTE structure is utilized to achieve a high blocking voltage with a wider optimum process latitude. A forward current is 50 A at room temperature when SiC PiN device bias 4.1 V, while the maximum blocking voltage achieved is 4.7 kV, reaching up to 86% of parallel-plane junction bulk breakdown.

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