Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

scholarly journals Towards a Glass New World: The Role of Ion-Exchange in Modern Technology

2021 ◽  
Vol 11 (10) ◽  
pp. 4610
Author(s):  
Simone Berneschi ◽  
Giancarlo C. Righini ◽  
Stefano Pelli
Keyword(s):  
Ion Exchange ◽  
Communication Networks ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Modern Technology ◽  
Historical Background ◽  
Wide Range ◽  
Happy Marriage

Glasses, in their different forms and compositions, have special properties that are not found in other materials. The combination of transparency and hardness at room temperature, combined with a suitable mechanical strength and excellent chemical durability, makes this material indispensable for many applications in different technological fields (as, for instance, the optical fibres which constitute the physical carrier for high-speed communication networks as well as the transducer for a wide range of high-performance sensors). For its part, ion-exchange from molten salts is a well-established, low-cost technology capable of modifying the chemical-physical properties of glass. The synergy between ion-exchange and glass has always been a happy marriage, from its ancient historical background for the realisation of wonderful artefacts, to the discovery of novel and fascinating solutions for modern technology (e.g., integrated optics). Getting inspiration from some hot topics related to the application context of this technique, the goal of this critical review is to show how ion-exchange in glass, far from being an obsolete process, can still have an important impact in everyday life, both at a merely commercial level as well as at that of frontier research.

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

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