scholarly journals Sixty Earth-Day Test of a Prototype Pt/HTCC Alumina Package in a Simulated Venus Environment

2019 ◽  
Vol 16 (2) ◽  
pp. 78-83 ◽  
Author(s):  
Liangyu Chen ◽  
Philip G. Neudeck ◽  
Roger D. Meredith ◽  
Dorothy Lukco ◽  
David J. Spry ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environment ◽  
Electrical Performance ◽  
Harsh Environment ◽  
Three Phase ◽  
Testing Environments ◽  
Earth Day ◽  
The Stability ◽  
Surface Environment

Abstract This article presents experimental results of a prototype high-temperature cofired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with a 60-d demonstration in a simulated Venus surface environment consisting of a 465°C corrosive atmosphere at 90 bar pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide high-temperature semiconductor integrated circuits in 500°C Earth air ambient for more than 10,000 hours, and short-term tested at temperatures above 800°C. The three-phase harsh environment test started with 48 h in 465°C Earth air, followed by 48 h in 465°C nitrogen at 90 bar pressure and 1,400 h in a simulated Venus surface environment of 465°C corrosive atmosphere at 90 bar. In addition to in situ electrical tests in a three-phase harsh environment and posttest electrical diagnosis, initial posttest analysis of the package materials and surfaces was performed to assess the stability of the packaging materials in the testing environments, as well as the surface conditions after the test. The test in the simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig. The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help improve the long-term electrical performance of an HTCC alumina packaging system in a Venus environment.

scholarly journals Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000015-000021
Author(s):  
Liangyu Chen ◽  
Philip G. Neudeck ◽  
Roger D. Meredith ◽  
Dorothy Lukco ◽  
David J. Spry ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Extreme Environment ◽  
Electrical Performance ◽  
Harsh Environment ◽  
Short Term ◽  
Packaging System ◽  
Three Phase ◽  
The Stability ◽  
Package Materials ◽  
Surface Environment

Abstract This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 °C with corrosive atmosphere at 90 bar pressure. The prototype package is based on previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 °C Earth air ambient for over ten thousands hours, and short-term tested at temperatures above 800 °C. The three-phase harsh environment test started with 48 hours in 465 °C Earth air, followed by 48 hours in 465 °C nitrogen at 90 bar pressure and 1400 hours in simulated Venus surface environment of 465 °C with corrosive atmosphere at 90 bar. Initial analytical results of the package materials and surfaces after exposure to Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

scholarly journals Study on the Stability of the Electrical Connection of High-Temperature Pressure Sensor Based on the Piezoresistive Effect of P-Type SiC

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 216
Author(s):  
Yongwei Li ◽  
Ting Liang ◽  
Cheng Lei ◽  
Qiang Li ◽  
Zhiqiang Li ◽  
...  
Keyword(s):  
High Temperature ◽  
Pressure Sensor ◽  
Pressure Sensors ◽  
Extreme Environment ◽  
Maximum Temperature ◽  
Piezoresistive Effect ◽  
Electrical Connection ◽  
Contact Stability ◽  
The Stability ◽  
P Type

In this study, a preparation method for the high-temperature pressure sensor based on the piezoresistive effect of p-type SiC is presented. The varistor with a positive trapezoidal shape was designed and etched innovatively to improve the contact stability between the metal and SiC varistor. Additionally, the excellent ohmic contact was formed by annealing at 950 °C between Ni/Al/Ni/Au and p-type SiC with a doping concentration of 1018cm−3. The aging sensor was tested for varistors in the air of 25 °C–600 °C. The resistance value of the varistors initially decreased and then increased with the increase of temperature and reached the minimum at ~450 °C. It could be calculated that the varistors at ~100 °C exhibited the maximum temperature coefficient of resistance (TCR) of ~−0.35%/°C. The above results indicated that the sensor had a stable electrical connection in the air environment of ≤600 °C. Finally, the encapsulated sensor was subjected to pressure/depressure tests at room temperature. The test results revealed that the sensor output sensitivity was approximately 1.09 mV/V/bar, which is better than other SiC pressure sensors. This study has a great significance for the test of mechanical parameters under the extreme environment of 600 °C.

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

2020 ◽  
Vol 1004 ◽  
pp. 1148-1155 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Carl W. Chang
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Extreme Temperature ◽  
Energy Systems ◽  
Extreme Environment ◽  
Air Atmosphere ◽  
Passivation Layers ◽  
Operating Lifetime ◽  
Effect Transistor

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Extreme Environment Integrated Circuits Based on Enhancement Mode SiC JFETs

2020 ◽  
Vol 1004 ◽  
pp. 1097-1103
Author(s):  
Peter Alexandrov ◽  
Matt O'Grady
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Ion Implantation ◽  
Analog Circuits ◽  
Operational Amplifier ◽  
Extreme Environment ◽  
Logic Circuits ◽  
Enhancement Mode ◽  
Temperature Capability ◽  
Ic Technology

This paper presents results on developing high temperature capable SiC JFET based IC technology that can operate at temperatures up to 500 °C. All JFET devices are fully planar, formed by ion implantation, and the device design allows the use of semi-insulating or conductive SiC substrates. Basic analog and logic ICs were built in order to demonstrate the technology high temperature capability. All circuits used enhancement mode n-channel JFETs as active transistors, and depletion mode transistors as active loads. The logic circuits built included NOT, NAND, and NOR gates. The analog circuits built included a simple one-stage operational amplifier. JFETs and ICs were packaged in ceramic packages and tested at temperatures up to 500 °C.

Electrical Performance of a 32-I/O HTCC Alumina Package for High-Temperature Microelectronics

2017 ◽  
Vol 14 (1) ◽  
pp. 11-16 ◽  
Author(s):  
Liang-Yu Chen ◽  
Philip G. Neudeck ◽  
David J. Spry ◽  
Glenn M. Beheim ◽  
Gary W. Hunter
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Parasitic Capacitance ◽  
Circuit Board ◽  
Electrical Performance ◽  
Packaging System ◽  
Dielectric Performance ◽  
Temperature Ranges ◽  
Parallel Conductance ◽  
Potential Use

A high-temperature cofired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550°C and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high-temperature packaging applications. This article introduces a prototype 32-input/output (I/O) HTCC alumina package with platinum conductor for 500°C low-power SiC-integrated circuits. The design and electrical performance of this package, including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550°C, are discussed in detail. The parasitic capacitance and parallel conductance of neighboring I/Os of this package in the entire frequency and temperature ranges measured do not exceed 1.5 pF and 0.05 μS, respectively. SiC-integrated circuits using this package and a compatible alumina circuit board have been successfully tested at 500°C for more than 3,736 h continuously, and at 700°C for more than 140 h. Some test examples of SiC-integrated circuits with this packaging system are presented.

scholarly journals Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000066-000072 ◽  
Author(s):  
Liang-Yu Chen ◽  
Philip G. Neudeck ◽  
David J. Spry ◽  
Glenn M. Beheim ◽  
Gary W. Hunter
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Parasitic Capacitance ◽  
Circuit Board ◽  
Electrical Performance ◽  
Operational Testing ◽  
Dielectric Performance ◽  
Temperature Ranges ◽  
Parallel Conductance

Abstract A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 °C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 °C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 °C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 μS, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 °C for over 3736 hours continuously, and at 700 °C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T ≥ 500 °C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics

2017 ◽  
Vol 897 ◽  
pp. 669-672 ◽  
Author(s):  
Shinichiro Kuroki ◽  
Tatsuya Kurose ◽  
Hirofumi Nagatsuma ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Leakage Current ◽  
High Voltage ◽  
Logic Gate ◽  
Harsh Environment ◽  
Test Elements ◽  
Voltage Swing

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

Effect of Improved ThO2 Particle Dispersion in Nickel on High-Temperature Strength

1970 ◽  
Vol 28 ◽  
pp. 444-445
Author(s):  
E. R. Kimmel ◽  
H. L. Anthony ◽  
W. Scheithauer
Keyword(s):  
High Temperature ◽  
Metal Matrix ◽  
Oxide Particle ◽  
Oxide Phase ◽  
Dislocation Motion ◽  
Particle Dispersion ◽  
High Temperature Strength ◽  
Strengthening Effect ◽  
Oxide Particles ◽  
The Stability

The strengthening effect at high temperature produced by a dispersed oxide phase in a metal matrix is seemingly dependent on at least two major contributors: oxide particle size and spatial distribution, and stability of the worked microstructure. These two are strongly interrelated. The stability of the microstructure is produced by polygonization of the worked structure forming low angle cell boundaries which become anchored by the dispersed oxide particles. The effect of the particles on strength is therefore twofold, in that they stabilize the worked microstructure and also hinder dislocation motion during loading.

Test of the stability of a three-phase contact line with negative line tension

1999 ◽  
Vol 96 (9) ◽  
pp. 1335-1339 ◽  
Author(s):  
ALAN E. VAN GIESSEN, DIRK JAN BUKMAN, B.
Keyword(s):  
Contact Line ◽  
Line Tension ◽  
Phase Contact ◽  
Three Phase ◽  
The Stability

An Alternative to High-Temperature and Acid/Solvent-Based Methods for Removing Integrated Circuits from Ceramic or Other Problem Substrates

2005 ◽  
Author(s):  
Carl M. Nail
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Success Rate ◽  
Mechanical Damage ◽  
Test Equipment ◽  
High Success Rate ◽  
Automated Test Equipment ◽  
Removal Method ◽  
Automated Test ◽  
Conventional Methods

Abstract Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.

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