Mechanical Robustness of Solder Connections to Thick Film Gold

2011 ◽  
Vol 2011 (1) ◽  
pp. 000327-000336
Author(s):  
Thomas F. Marinis ◽  
Joseph W. Soucy
Keyword(s):  
Thick Film ◽  
High Reliability ◽  
Accelerated Aging ◽  
Element Analysis ◽  
Bga Packages ◽  
Fine Pitch ◽  
Solder Balls ◽  
Lift Off ◽  
Extended Area ◽  
Gold Metallization

Thick film gold metallization is required for many high reliability circuits, especially those subjected to operation in high temperature or high humidity environments. Traditionally, wire bonded bare die are used on these circuits, but there is a trend to replace them with BGA packaged devices. State-of-the-art, chip scale packages increase circuit volume by less than 20 percent, while their use greatly simplifies testing and repair, as compared to wire bonded die. The use of small, high density I/O pad arrays for attachment of BGA packages, necessitates very careful control of the solder reflow process to avoid excessive leaching of the gold into the solder. Also, unlike passive chip components and leaded devices, the solder filet associated with a solder ball attachment does not distribute mechanical loads over an extended area. Consequently, the stresses imposed on fine pitch, BGA pads are much higher than those imposed by other components. During aging, the gold metallization is converted to gold-tin intermetallic as inter-diffusion proceeds. This further reduces the mechanical integrity of the solder connection. This manifests itself in the observation that when BGA solder balls are subjected to accelerated aging followed by shear testing, the entire solder pad lifts off of the substrate, rather than failing in the solder joint. What we have done is construct a diffusion based model to estimate the conversion of a thick film gold metallization pad to intermetallic and coupled this result with a finite element analysis to examine the effect of pad size and solder composition on the propensity of a pad to lift off the substrate, when subjected to mechanical or thermal induced loading. We are designing experiments to compare the predictions of our model to experimental results obtained from shearing solder balls, of different compositions and sizes, attached to substrates metalized with several different solderable, thick film gold materials.

Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects

2010 ◽  
Vol 2010 (1) ◽  
pp. 000298-000305
Author(s):  
Tae-Kyu Lee ◽  
Weidong Xie ◽  
Thomas R. Bieler ◽  
Kuo-Chuan Liu ◽  
Jie Xue
Keyword(s):  
Thermal Cycling ◽  
Microstructure Evolution ◽  
Isothermal Aging ◽  
Substrate Surface ◽  
Solder Interconnects ◽  
Surface Finishes ◽  
Bga Packages ◽  
Fine Pitch ◽  
Solder Balls

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Simulation Study of Magnetic Memory Signal Correlation Effect of Dual Defects by ANSYS

2014 ◽  
Vol 989-994 ◽  
pp. 3189-3194
Author(s):  
Xiao Wen Xi ◽  
Shang Kun Ren ◽  
Ya Fan Zhang ◽  
Yin Huang
Keyword(s):  
Stress Concentration ◽  
High Reliability ◽  
Normal Component ◽  
Tensile Load ◽  
Steel Specimen ◽  
Correlation Effect ◽  
Magnetic Memory ◽  
Element Analysis ◽  
Obvious Effect ◽  
Lift Off

To study the correlation effect of multiple defects of metal magnetic memory (MMM) testing technology, the stress-magnetization effect on 20# steel specimen with dual defects under exercise of the geomagnetic field and tensile load is simulated by using the finite element analysis (FEA) software ANSYS. With the stimulation, the magnetic flux leakage (MFL) distribution with different measured paths and different lift-off values of the surface specimen is given. The results showed that the correlation effect of dual defects produce more severe stress concentration phenomenon on the associated region of ferromagnetic specimen, and had no obvious effect on the edge of ferromagnetic materials; Gradient value K of the normal component H(z) of leakage magnetic field in the specimen, as a parameter evaluation of stress concentration in the specimen, has high reliability in areas without correlation effect, but it has no credibility in areas under dual defect correlation effect. Moreover, this article also discusses the influence of measured path and the lift-off value on magnetic memory signals.

Lifetime Prediction of Tires with Regard to Oxidative Aging5

2008 ◽  
Vol 36 (1) ◽  
pp. 63-79 ◽  
Author(s):  
L. Nasdala ◽  
Y. Wei ◽  
H. Rothert ◽  
M. Kaliske
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Temperature Distribution ◽  
Superposition Principle ◽  
Accelerated Aging ◽  
Material Model ◽  
Aging Behavior ◽  
Element Analysis ◽  
Material Parameters ◽  
Reaction Processes

Abstract It is a challenging task in the design of automobile tires to predict lifetime and performance on the basis of numerical simulations. Several factors have to be taken into account to correctly estimate the aging behavior. This paper focuses on oxygen reaction processes which, apart from mechanical and thermal aspects, effect the tire durability. The material parameters needed to describe the temperature-dependent oxygen diffusion and reaction processes are derived by means of the time–temperature–superposition principle from modulus profiling tests. These experiments are designed to examine the diffusion-limited oxidation (DLO) effect which occurs when accelerated aging tests are performed. For the cord-reinforced rubber composites, homogenization techniques are adopted to obtain effective material parameters (diffusivities and reaction constants). The selection and arrangement of rubber components influence the temperature distribution and the oxygen penetration depth which impact tire durability. The goal of this paper is to establish a finite element analysis based criterion to predict lifetime with respect to oxidative aging. The finite element analysis is carried out in three stages. First the heat generation rate distribution is calculated using a viscoelastic material model. Then the temperature distribution can be determined. In the third step we evaluate the oxygen distribution or rather the oxygen consumption rate, which is a measure for the tire lifetime. Thus, the aging behavior of different kinds of tires can be compared. Numerical examples show how diffusivities, reaction coefficients, and temperature influence the durability of different tire parts. It is found that due to the DLO effect, some interior parts may age slower even if the temperature is increased.

Method of Detecting Trace Metal Contamination in Thick-Film SOI Device

2005 ◽  
Author(s):  
Yasunori Goto ◽  
Hiroomi Eguchi ◽  
Masaru Iida
Keyword(s):  
Trace Metal ◽  
Thick Film ◽  
Metal Contamination ◽  
Semiconductor Device ◽  
Trace Element Analysis ◽  
Silicon On Insulator ◽  
Element Analysis ◽  
Trace Metal Contamination ◽  
Trace Metal Elements ◽  
Output Characteristics

Abstract In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.

Reaction kinetics of solder-balls with pads in BGA packages during reflow soldering

1999 ◽  
Vol 28 (11) ◽  
pp. 1231-1237 ◽  
Author(s):  
C. E. Ho ◽  
Y. M. Chen ◽  
C. R. Kao
Keyword(s):  
Reaction Kinetics ◽  
Reflow Soldering ◽  
Bga Packages ◽  
Solder Balls ◽  
Kinetics Of

scholarly journals Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

2019 ◽  
Vol 16 (2) ◽  
pp. 91-102
Author(s):  
Lars Bruno ◽  
Benny Gustafson
Keyword(s):  
Solder Joints ◽  
Solder Paste ◽  
Wafer Level ◽  
Reflow Soldering ◽  
X Ray ◽  
Soldering Process ◽  
Irregular Shapes ◽  
Fine Pitch ◽  
Solder Balls ◽  
Ball Grid Array Packages

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga
Keyword(s):  
Thin Film ◽  
Thick Film ◽  
Screen Printing ◽  
Flip Chip ◽  
High Density ◽  
Uv Laser ◽  
Fine Pitch ◽  
Ink Jet ◽  
Printing Ink ◽  
Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)

2012 ◽  
Vol 2012 (1) ◽  
pp. 001137-001142 ◽  
Author(s):  
Ilyas Mohammed
Keyword(s):  
High Performance ◽  
Copper Interconnects ◽  
Free Standing ◽  
Positional Accuracy ◽  
Aspect Ratios ◽  
Fine Pitch ◽  
Wire Bonds ◽  
Solder Balls ◽  
The Wire ◽  
Interconnect Technology

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

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