SiP Drivers and Challenges: Supply Chain Outlook and Requirements

2015 ◽  
Vol 2015 (S2) ◽  
pp. S1-S21
Author(s):  
Linda Bal
Keyword(s):  
Supply Chain ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Functional System ◽  
Next Generation ◽  
Wafer Level ◽  
Mechanical Parts ◽  
Close Proximity ◽  
And Performance

Cost pressures are driving the semiconductor industry to look for solutions that meet the challenge of expensive next generation silicon node fabrication. Simply integrating all functions in a single die may no longer be the most economical option. In addition, the need for close proximity of die and components has driven the development of packages that provide both the price and performance needs. System-in-Package (SiP) is gaining popularity as one of the most promising integration solutions. SiP is a functional system or subsystem assembled into a single package. It may contain two or more dissimilar die, typically combined with other components such as passives, filters, antennas, and/or mechanical parts. The components are mounted together on a substrate to create a customized, highly integrated product for a given application. SiPs may utilize a combination of wire bond, flip chip, wafer level packages, pre-packaged ICs such as CSPs, stacked packages, and/or stacked die. This presentation examines the role of system-in-package (SiP) discussing the formats most likely to emerge as volume packages and the supply chain requirements to produce these packages. The roles of OSATs and EMS companies are discussed with a discussion on the advantages and challenges of each.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

scholarly journals Improving retail supply flexibility using buyer-supplier relational capabilities

2017 ◽  
Vol 37 (3) ◽  
pp. 343-362 ◽  
Author(s):  
Raymond Obayi ◽  
S.C. Koh ◽  
David Oglethorpe ◽  
Seyed M. Ebrahimi
Keyword(s):  
Supply Chain ◽  
Supplier Relationships ◽  
Chain Flexibility ◽  
Content Type ◽  
Mediating Role ◽  
Supply Chain Flexibility ◽  
And Performance ◽  
Relational Capabilities ◽  
Practical Implications

Purpose The purpose of this paper is to investigate the mediating role of three important relational capabilities – absorptive capacity (AC), transactive memory systems (TMS), and organisational interoperability (OI); on the flexibility of buyer-supplier relationships and performance in retail supply chains. Drawing on the relational view of strategic management, the impact of relational capabilities on two forms of supply chain flexibility is examined – configuration flexibility (CF) for switching suppliers with minimal penalties, and planning and control flexibility (PCF) for altering supply schedules, quality, and delivery lead-time. Design/methodology/approach Strategic- and tactical-level managers from 211 retail stores in the UK were surveyed. The authors validated a measurement model with structural equation modelling and tested four hypotheses on the mediating role of relational capabilities on supply chain flexibility and retail performance, controlling for size, duration of relationship, and market segment. Findings Results showed that the three relational capabilities partially mediated the positive effect of CF and PCF on operational performance in big middle and niche retailers. Examining the interaction effect of the forms of flexibility on the relational capabilities and performance, the authors found positive interaction effects on TMS and OI but a non-significant effect on AC. Practical implications In addition to providing novel theoretical insights on supply chain flexibility, the findings have practical implications for supplier selection and buyer-supplier relationship management. Originality/value Overall, the study highlights the impacts of relational capabilities on adopted operational strategies such as flexibility, buyer-supplier relationships, and retail performance.

The Role of Knowledge Transfer in Supply Chain Flexibility and Performance

2018 ◽  
pp. 465-485 ◽  
Author(s):  
José Roberto Díaz-Reza ◽  
Valeria Martínez-Loya ◽  
Jorge Luis García Alcaraz ◽  
Ismael Canales-Valdiviezo
Keyword(s):  
Supply Chain ◽  
Knowledge Transfer ◽  
Chain Flexibility ◽  
Supply Chain Flexibility ◽  
And Performance

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

B2B e-commerce supply chain integration and performance: A contingency fit perspective on the role of environment

2009 ◽  
Vol 46 (6) ◽  
pp. 313-322 ◽  
Author(s):  
Karthik N.S. Iyer ◽  
Richard Germain ◽  
Cindy Claycomb
Keyword(s):  
Supply Chain ◽  
Supply Chain Integration ◽  
And Performance
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