Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

2015 ◽  
Vol 2015 (1) ◽  
pp. 000793-000798
Author(s):  
Keith Best ◽  
Roger McCleary ◽  
Richard Hollman ◽  
Phillip Holmes
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Performance ◽  
Flip Chip ◽  
Technology Development ◽  
Semiconductor Industry ◽  
Scale Up ◽  
Wafer Level ◽  
Integration Schemes ◽  
Advanced Packaging

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36 ◽  
Author(s):  
Elvino Da Silveira ◽  
Keith Best ◽  
Gurvinder Singh ◽  
Roger McCleary
Keyword(s):  
Cost Reduction ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Main Driver ◽  
Ratio Imaging ◽  
Advanced Packaging ◽  
High Yields ◽  
Line Space

For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Panel fan out Packaging. The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

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