Hermetic Seal Bonding at Low-temperature with Sub-micron Gold Particles for Wafer Level Packaging

Au/Au hermetic sealing was successfully done using a rim structure covered with sub-micron-size Au particles by low-temperature thermo-compression bonding. The easy deformability of sintered Au particles is advantageous in terms of the compliance with surface irregularity as well as the insensitivity of surface flatness. From the deflection of Si diaphragms over the sealed cavity, an inside pressure of 100 Pa and the maximum leak rate in a range of 10−14 Pa·m3/s (He) were estimated, which is sufficient for many MEMS applications.

Download Full-text

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems ◽

10.1115/micronano2008-70288 ◽

2008 ◽

Author(s):

James Lee ◽

Tony Rogers

Keyword(s):

Low Temperature ◽

Wafer Bonding ◽

High Strength ◽

Mems Devices ◽

Wafer Level ◽

Direct Bond ◽

Hermetic Packaging ◽

Wafer Level Packaging ◽

Hermetic Seal ◽

Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

Download Full-text

Reliability of Hermetic RF MEMS Wafer Level Packaging Using Au-Sn Eutectic Bonding

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.326-328.609 ◽

2006 ◽

Vol 326-328 ◽

pp. 609-612

Author(s):

Qian Wang ◽

Sung Hoon Choa ◽

Woon Bae Kim ◽

Jun Sik Hwang ◽

Suk Jin Ham ◽

...

Keyword(s):

Shear Strength ◽

Low Temperature ◽

Insertion Loss ◽

Rf Mems ◽

Wafer Level ◽

Eutectic Bonding ◽

Wafer Level Packaging ◽

Hermetic Sealing ◽

Multilayer Metallization

In this paper, a low temperature hermetic wafer level packaging scheme for the RFMEMS devices is presented. For hermetic sealing, Au-Sn multilayer metallization with a square loop of 70 %m in width is performed. The size of the MEMS package is 1mm × 1mm × 700 %m. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. The total insertion loss for the packaging is 0.075 dB at 2 GHz.

Download Full-text

Low Temperature Al-Al Thermo-compression Bonding with Sn Oxidation Protect Layer for Wafer-level Hermetic Sealing

IEEJ Transactions on Sensors and Micromachines ◽

10.1541/ieejsmas.136.237 ◽

2016 ◽

Vol 136 (6) ◽

pp. 237-243 ◽

Cited By ~ 2

Author(s):

Shiro Satoh ◽

Hideyuki Fukushi ◽

Masayoshi Esashi ◽

Shuji Tanaka

Keyword(s):

Low Temperature ◽

Wafer Level ◽

Hermetic Sealing

Download Full-text

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

MRS Proceedings ◽

10.1557/proc-729-u5.7 ◽

2002 ◽

Vol 729 ◽

Cited By ~ 3

Author(s):

Lauren E. S. Rohwer ◽

Andrew D. Oliver ◽

Melissa V. Collins

Keyword(s):

Shear Strength ◽

Test Sample ◽

Anodic Bonding ◽

Mems Devices ◽

Wafer Level ◽

Thermal Actuators ◽

Wafer Level Packaging ◽

Hermetic Seal ◽

Leak Testing ◽

Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

Download Full-text

Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

Proceedings Electronic Components and Technology, 2005. ECTC '05. ◽

10.1109/ectc.2005.1441323 ◽

2005 ◽

Cited By ~ 4

Author(s):

J. Leib ◽

D. Mund ◽

M. Topper

Keyword(s):

Low Temperature ◽

Wafer Level ◽

Packaging Technology ◽

Wafer Level Packaging

Download Full-text

Low temperature direct bonding for hermetic wafer level packaging

2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems ◽

10.1109/nems.2009.5068621 ◽

2009 ◽

Author(s):

Lei Nie ◽

Tielin Shi ◽

Zirong Tang ◽

Shiyuan Liu ◽

Guanglan Liao

Keyword(s):

Low Temperature ◽

Wafer Level ◽

Wafer Level Packaging

Download Full-text

Wafer Level Package for MEMS with TSVs and Hermetic Seal

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tha24 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 002314-002335

Author(s):

Akinori Shiraishi ◽

Mitsutoshi Higashi ◽

Kei Murayama ◽

Yuichi Taguchi ◽

Kenichi Mori

Keyword(s):

Silicon Wafer ◽

Adhesive Bonding ◽

Anodic Bonding ◽

Back Side ◽

Wafer Level ◽

Wafer Level Packaging ◽

Hermetic Seal ◽

Mems Device ◽

Bonding Method ◽

Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Download Full-text