Voiding Control at Preform Soldering

2016 ◽  
Vol 2016 (1) ◽  
pp. 000630-000637
Author(s):  
Arnab Dasgupta ◽  
Elaina Zito ◽  
Ning-Cheng Lee

Abstract Assembly of components with large pads such as high brightness LEDs or high power dies often is soldered with preform, mainly due to a lower voiding and lower flux fume generated when compared with solder paste, and also because of its better thermal and electrical conductivity compared with Ag epoxy. This is particularly true when the joints are to be formed within a cavity. Although lower than solder paste, the voiding in the solder joint is still a concern for high reliability and high performance devices. In this study, voiding at high power die attach reflow soldering using preform was simulated with the use of Cu coupons to mimic both die and substrate. The voiding behavior was studied by varying solder alloy type, flux quantity coated on preform, oxidation extent of Cu coupon, reflow peak temperature, and weight applied on the top of simulated die. For SAC305, with increasing weight, the bondline thickness (BLT) maintained constant initially due to solder surface tension, then reduced rapidly at weight higher than 50 g. The voiding area % increased with decreasing BLT first, then levelled off at lower BLT, although the voiding volume decreased with decreasing BLT due to constrained lamellar solder flow. Voiding was the highest for SAC305, followed by 57Bi42Sn1Ag, with 63Sn37Pb being the lowest, and increased with increasing oxidation of Cu coupon. With increasing flux quantity, voiding increased for SAC305 and 63Sn37Pb, but decreased for 57Bi42Sn1Ag, mainly due to the different temperature range at reflow. Voiding increased with increasing reflow temperature up to 170°C due to increasing vaporization, decreased with further increase in reflow temperature up to 210°C due to increasing flux activity, and increased again at temperature beyond 210°C due to rapid flux outgassing.

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000051-000055
Author(s):  
Maciej Patelka ◽  
Nicholas Krasco ◽  
Sho Ikeda ◽  
Toshiyuki Sato ◽  
Miguel Goni ◽  
...  

Abstract High power semiconductor applications require a die attach material with high thermal conductivity to efficiently release the heat generated from these devices. Current die attach solutions such as eutectic solders and high thermal conductive silver epoxies and sintered silver adhesives have been industry standards, however may fall short in performance for high temperature or high stress applications. This presentation will focus on development of a reinforced, sintered silver die attach solution for high power semiconductor applications with focus on a pressure-less, low temperature sintering technology that offers high reliability for high temperature (250°C) applications. The electronic, optoelectronic, and semiconductor industries have the need for high performance adhesives, in particular, high power devices require low-stress, high thermal conductivity, thermally stable, and moisture resistant adhesives for the manufacture of high reliability devices. This paper introduces a new reinforced sintered silver adhesive based on the “resin-free” Conductive Fusion Technology. The high performance adhesive offers a robust solution for high temperature, high reliability applications. Conductive Fusion Technology consists of a high thermal conductivity silver component blended with a non-conductive, low-modulus powder component. The non-conductive powder component comprises an organically modified inorganic material that exhibits excellent thermal stability at temperatures exceeding 250°C. Properties of the sintered silver adhesive, such as storage modulus, can be modified by varying the content of the non-conductive component.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000136-000141 ◽  
Author(s):  
Amanda Hartnett ◽  
Seth Homer ◽  
Donald Beck ◽  
Daniel Evans

High-power semiconductor devices, such as high-brightness Light Emitting Diodes (LEDs), must be mounted using a robust adhesive material to handle the temperature fluctuations generated by the chip and the mechanical stresses due to the coefficient of thermal expansion (CTE) mismatches between the die material and substrate it is mounted to. The selected material must also comply with current legislation restricting manufactured products containing numerous materials including some that were historically popular in HB LED applications due to environmental concerns. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented in this paper. Utilizing a Palomar Technologies die bonder, AuSn solder preforms and paste will be placed/dispensed and reflowed using a Pulsed Heat System (PHS). Evaluation methods comparing these means of eutectic die attach to a pre-plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test methods as well as hypotheses of results.


2007 ◽  
Author(s):  
Dan A. Yanson ◽  
John H. Marsh ◽  
Stephen Najda ◽  
Stewart D. McDougall ◽  
Hassan Fadli ◽  
...  

2022 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Daniel Straubinger ◽  
Attila Toth ◽  
Viktor Kerek ◽  
Zsolt Czeczei ◽  
Andras Szabo ◽  
...  

Purpose The purpose of this paper is to study the solder beading phenomenon (referring to larger-sized solder balls) of surface-mounted electrolytic capacitors. Solder beading could induce failures by violating the minimal electrical clearance on the printed circuit board (PCB). In modern lead-free reflow soldering, especially in high-reliability industries, such as automotive, aeroplane and aerospace, detecting and preventing such defects is essential in reliable and cost-effective manufacturing. Design/methodology/approach The large size of the involved components may block the view of automatic optical inspection; therefore, X-ray inspection is necessary. To detect the failure mode, X-ray imaging, cross-section grinding, optical microscopy and Fourier transformed infrared spectroscopy were used. High-resolution noncontact profilometry and optical microscopy were used to analyse component designs. The surface mounting process steps were also analysed to reveal their dependence on the issue. Test methods were designed and performed to reveal the behaviour of the solder paste (SP) during the reflow soldering process and to emphasise the component design relevance. Findings It was found that the reduction of SP volume only reduces the failure rate but does not solve the problem. Results show that excessive component placement pressure could induce solder beading. Statistical analysis revealed that differences between distinct components had the highest effect on the solder beading rate. Design aspects of solder beading-prone components were identified and discussed as the primary source of the problem. Practical implications The findings can be applied in surface-mount technology production, where the total failure count and resulting failure costs could be reduced according to the findings. Originality/value This paper shows that component design aspects such as the low distance between the underside of the component and the PCB and blocked proper outgassing of volatile compounds of the SP can be root causes of solder beading under surface-mounted electrolytic capacitors.


2015 ◽  
Author(s):  
L. Bao ◽  
M. Kanskar ◽  
M. DeVito ◽  
M. Hemenway ◽  
W. Urbanek ◽  
...  

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000213-000217
Author(s):  
Tiago M. L. Teixeira ◽  
Juan Bevan

Abstract: The goal of this study was to achieve an improvement on power conversion based on SiC High Power Electronic devices at high temperature (+220°C). Two different devices (a SiC Schottky Diode & a Schottky Diode Bridge Rectifier) were studied using different substrates, die attach materials and die. Positive results were achieved; it was found a strong relationship between wire bond strength and die attach material; it was evident the two different die chosen for the study resulted in different electrical performance on the devices; and that, from the arrays of tests, there was no evident data to prefer one of the two substrates chosen for the study.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000654-000660 ◽  
Author(s):  
Fang Yu ◽  
R. Wayne Johnson ◽  
Michael C. Hamilton

With an increasing demand for SiC and GaN high power devices that operate at high temperature, traditional solder materials are reaching their limitations in performance. In addition, there is a strong desire to eliminate high lead containing solders in Si power device packaging for use over conventional temperature range. Low temperature Ag sintering technology is a promising method for high performance lead-free die attachment. In a previous study, a pressureless sintering process and suitable metallization were demonstrated to provide high reliability die attach by using micro-size Ag sintering. The resulting die attach layer had approximately 30% porosity. In this work, a low temperature pressure-assisted fast sintering process was examined. The porosity was decreased from 30% to 15% with application of a low pressure (7.6MPa) during a one minute sintering process. The shear strength for a 3 mm × 3 mm die was 70 MPa and the 8 mm × 8 mm die could not be sheared off due to a 100 kg shear module force limit. Both the Ag and Au metallization (die and substrate) were studied. Furthermore, a new substrate metallization combination was found that allows the use of Au thick film metallized substrates. High temperature (300 °C) storage tests for up to 2000 hours aging were conducted and results are presented.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000482-000490
Author(s):  
Eiji Yamaguchi ◽  
Mutsuo Tsuji ◽  
Nozomi Shimoishizaka ◽  
Takahiro Nakano ◽  
Katsunori Hirata

As the current and next generation devices are embracing geometries below 28nm and requiring softer low-K dielectric isolation on very thin large silicon dies ∼ to perform a reliable die-to-package interconnect is becoming a challenge. Further, the high pressure from Cu wire bonding and high reflow temperature of conventional flip-chip bonding often results in damage of device structure. A new flip-chip bonding technology has been developed for such critical applications, and is claimed to be “damage free”. It uses soft bump made by non-full cured conductive paste on the package substrate. These soft bumps require ultra-low bonding pressure on the pad of the die. Thus the bonding process don't make any damage on ULK isolation layer. Details of the process, material sets used for such fragile device structures have been discussed. Reliability results are shared, which further ensures the robustness of this process. Finally, the cost advantage through adaptation of this process has also been elaborated.


2014 ◽  
Author(s):  
M. Kanskar ◽  
L. Bao ◽  
J. Bai ◽  
Z. Chen ◽  
D. Dahlen ◽  
...  

1995 ◽  
Vol 05 (03) ◽  
pp. 503-521 ◽  
Author(s):  
LOURENCO MATAKAS ◽  
CATALIN BURLACU ◽  
EISUKE MASADA

Recently, there is an increased demand for high power, high performance converters for power system applications, motor drives, etc. The low switching frequency of the existing semiconductor power devices poses a severe limitation that can be overcome by the use of interconnected smaller power converters (multiconverter) with appropriate control. This paper gives an overview of the state of the art of multiconverters, followed by a comparison based on analytically calculated values of the spectra, RMS and peak values of their ripple currents, and the peak values of the transformer's flux. Special attention has been given to show that the transformerless parallel connection of converters is feasible and offers features such as simplicity, gracefully degrading operating, high reliability, easy expandability and easy maintenance.


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