Manufacturing Readiness of BVA™ Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (1) ◽  
pp. 000024-000030 ◽  
Author(s):  
Rajesh Katkar ◽  
Rey Co ◽  
Wael Zohni
Keyword(s):  
Aspect Ratio ◽  
Smart Phone ◽  
Cost Effective ◽  
High Volume ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
Vertical Interconnects ◽  
Reliability Performance ◽  
Manufacturing Readiness

Ever increasing performance demands in a rapidly evolving smart phone market have led to a need for higher density interconnections linking memory components with logic devices in a standard package on package (PoP) configuration. While existing solutions present a technological roadblock at 350–400μm PoP pitch, new Bond Via Array (BVA™) technology provides a cost effective and scalable alternative that can achieve 240μm and below pitch values while utilizing conventional wirebond package assembly processes and tools. BVA is a high density, ultra-fine pitch package-on-package (PoP) interconnect solution that enables more than 1000 high aspect ratio connections between memory and processor components in a standard outline PoP. This increase significantly improves PoP capability and correspondingly provides increased bandwidth for the next generation of mobile devices. Here we discuss the 1020 IO BVA demonstration test vehicle, associated manufacturing process details, reliability performance and bi-level socket hardware developed to test these wire bond based novel interconnects. Furthermore the overall high volume manufacturing (HVM) readiness state of this technology for PoP applications will be described. The 1020 IO BVA prototype features 5 rows of vertical interconnects at 0.24mm pitch within an industry standard 14 x14mm package footprint. Although BVA interconnects were primarily developed for PoP packages, they offer many benefits over traditional vertical interconnects and can be implemented in a variety of other applications.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000930-000959
Author(s):  
Wael Zohni ◽  
Rajesh Katkar ◽  
Rey Co ◽  
Rizza Cizek
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Volume ◽  
Third Party ◽  
High Yield ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Manufacturing Readiness

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Applying system modeling to define 2.5 - d and 3 - d packaging roadmaps

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001983-002007
Author(s):  
Dev Gupta
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
System Modeling ◽  
New Technology ◽  
Smart Phone ◽  
Cost Effective ◽  
High Volume ◽  
Organic Substrate ◽  
Chip Technology ◽  
D Modules

Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e,g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e,g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e,g. processor - memory modules to more performance driven and cost insensitive applications e,g. heterogeneous modules for electro - optic I/O in servers etc. Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance ( electrical ) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies. A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption ( two of the key drivers for die stacking ) of various 2.5-d and 3-d package configurations and based on simulation results compare them. Key takeaways : 3-d stacking of dice using TSVs may not necessarily produce improved performance compared to less complicated packaging. Expensive interposers with high interconnect density may not even be necessary for most volume applications. Most likely configurations for processor - memory 3-d modules to get good enough bandwidth at lowest cost.

PMV (Plating Mold Via) interconnection development in molded SiP modules

2014 ◽  
Vol 2014 (1) ◽  
pp. 000777-000782
Author(s):  
Do-Jae Yoo ◽  
Jong-In Ryu ◽  
Gyu-Hwan Oh ◽  
Yong-Choon Park ◽  
Ki-Ju Lee ◽  
...  
Keyword(s):  
Electronic Device ◽  
Smart Phone ◽  
Interfacial Strength ◽  
Test Vehicle ◽  
Soldering Process ◽  
Flip Chips ◽  
Fine Pitch ◽  
Wearable Electronic Device ◽  
Wearable Electronic ◽  
Packaging Module

Recently, there are increasing demands of a size reduction and a fine interconnection technology, especially for System-in-Package (SiP) module and Package on Package (POP) module in a smart phone and a wearable electronic device. In this study, we presented the Plating Mold Via (PMV) interconnection technology as an innovative fine pitch interconnection solution between substrate I/O pads and package I/O pads in molded System-in-Package (SiP) modules. Similar to the Through Mold Via (TMV), the laser mold via process is first performed to produce a through-via in the Epoxy Mold Compound (EMC) mold, but plating and Soldering process are used simultaneously to produce the metallurgical interconnection to embody the I/O pins of the over-molded surface. After the PMV technology is described, a study of PMV in the molded packaging module is followed. The study is conducted using a test vehicle of SiP module that contains flip chips, Quad Flat Non-leaded (QFN) packages and passives. It is focused on several interface reliability issues, including the interfacial strength of PMV to substrate metal pad as well as to the laser projected area of EMC, and the study of IMC at the plating metal and solder interfaces. The study clearly shows that the PMV technology is a promising fine pitch interconnect solution for various SiP modules.

Cost-effective, high-volume molecular beam epitaxy using a multi 6-in wafer reactor

2001 ◽  
Vol 227-228 ◽  
pp. 143-149
Author(s):  
Larry Leung ◽  
Damian Davison ◽  
Arthur Cornfeld ◽  
Frederick Towner ◽  
Dave Hartzell
Keyword(s):  
Molecular Beam Epitaxy ◽  
Molecular Beam ◽  
Cost Effective ◽  
High Volume

scholarly journals Microstructural Dependency of Diffusion in Glass Flake-Reinforced Vinyl Ester Resins

2012 ◽  
Vol 12 (1) ◽  
pp. 11 ◽  
Author(s):  
Bryan B. Pajarito ◽  
Masatoshi Kubouchi ◽  
Hiroyuki Tomita ◽  
Saiko Aoki
Keyword(s):  
Random Walk ◽  
Aspect Ratio ◽  
Vinyl Ester ◽  
Volume Fraction ◽  
Chemical Diffusion ◽  
High Volume ◽  
Diffusion Models ◽  
Simple Diffusion ◽  
Glass Flake ◽  
Vinyl Ester Resins

Vinyl ester resins are utilized for long-term corrosion protection of metal, alloy, and concrete substrates against concentrated acids, alkalis, and solvents at high temperature. Glass flakes are usually added as fillers to reduce chemical diffusion within the vinyl ester matrix. A common industry practice is to use glass flakes with large aspect ratio, high volume fraction, and in parallel alignment to surface in chemical contact for barrier applications. During processing and curing of glass flake-filled vinyl ester resins, irregular microstructures such as reduced flake aspect ratio and random orientation of flakes are commonly observed. Such microstructures can affect the overall chemical diffusion, resulting to barrier properties less predictable by simple diffusion models. Therefore, in this study, a simple 2D random walk simulation procedure is used in attempt to estimate the microstructural dependency of diffusion in glass flake-reinforced vinyl ester resins. While the random walk simulations are in good agreement with the tortuosity-based diffusion models in terms of microstructural effects, in most cases the simulation results are inconsistent with the experimental measurements of acid diffusion in glass flake-filled vinyl ester resins. A possible cause for this is the poor adherence of vinyl ester resin to glass flakes. Osmotic cracks are also formed during immersion which also influences overall diffusion through the material.

scholarly journals Development of High Volume Fly Ash Concrete Incorporating Steel Fibre

2020 ◽  
Vol 9 (2) ◽  
pp. 426-433
Keyword(s):  
Fly Ash ◽  
Aspect Ratio ◽  
Thermal Power ◽  
High Volume ◽  
Fine Aggregate ◽  
Fly Ash Concrete ◽  
High Volume Fly Ash ◽  
Hardened Properties ◽  
Very High ◽  
Split Tensile Test

Concrete is most frequently used composite material. Concrete is homogeneous mix of fine aggregate, Coarse aggregate and binding medium of concrete paste .Due to `high demand of cement Co2 emission is very high, It leads to global warming. So in this project high volume fly ash concrete was incorporated. Fly ash is the waste material obtained from thermal power plant. In this paper we investigated about high volume fly ash in different percentage of replacement 55, 60, 75 percentage. Layered pavement is incorporated with Steel fiber in a different aspect ratio (15, 30, 40).layered pavement will give good thermal expansive properties. By varying fly ash content and Steel fibers Aspect ratio of different mixes were arrived hardened properties of these nine mixes were arrived such as Compression test, Split tensile test and Flexural test.

ChipsetT: Embedded Die Substrate Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000377-000397
Author(s):  
Jon G. Aday ◽  
Ted Tessier ◽  
Kazuhisa Itoi ◽  
Satoshi Okude
Keyword(s):  
Large Scale ◽  
Cost Effective ◽  
Scale Production ◽  
Robust Solution ◽  
Sintered Metal ◽  
Design Flexibility ◽  
Fine Pitch ◽  
Large Scale Production ◽  
Bottom Side ◽  
Board Level

Embedded die substrate technologies are being developed in an assortment of configurations and for different market segments. The technology being discussed in this paper will be focused on both a fan out technology – ChipsetT Fan-Out and a system in package approach (ChipsetT SiP) in which a multiple component bill of materials (BOM) is used. The Chipset process is based on the WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multilayer polyimide flex wiring and conductive z-axis sintered metal interconnections. This ChipsetT Fan Out technology allows for large scale production of fan out type solutions which can allow for very thin packages in addition to unique pin out solutions such as pin compatibility for a competitor part. The ChipsetT SiP also allows embedding of single or multiple silicon die and/or components. Additional components can also be placed using conventional SMT on the top or bottom side of the package. There is a great deal of design flexibility with this technology which makes it a great solution for applications trying to reduce their x-y size or z-height. When utilizing RDL technology on the embedded die we are able to do the fine pitch routing in order to allow the substrate to route at larger pitches ensuring an overall cost effective solution. This paper will focus on the different classes of applications that have benefited from this technology and will discuss the benefits and tradeoffs of the different solutions that have been engineered. Assembly and reliability data will be presented on several of the applications showing a robust solution set.

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