scholarly journals Exploring the Effect of Device Aging on Static Power Analysis Attacks

2019 ◽  
pp. 233-256
Author(s):  
Naghmeh Karimi ◽  
Thorben Moos ◽  
Amir Moradi
Keyword(s):  
Power Analysis ◽  
Point Of View ◽  
Operating Conditions ◽  
Positive Development ◽  
Side Channel ◽  
Power Analysis Attacks ◽  
Future Technology ◽  
Static Power ◽  
Device Aging ◽  
The Impact

Vulnerability of cryptographic devices to side-channel analysis attacks, and in particular power analysis attacks has been extensively studied in the recent years. Among them, static power analysis attacks have become relevant with moving towards smaller technology nodes for which the static power is comparable to the dynamic power of a chip, or even dominant in future technology generations. The magnitude of the static power of a chip depends on the physical characteristics of transistors (e.g., the dimensions) as well as operating conditions (e.g., the temperature) and the electrical specifications such as the threshold voltage. In fact, the electrical specifications of transistors deviate from their originally intended ones during device lifetime due to aging mechanisms. Although device aging has been extensively investigated from reliability point of view, the impact of aging on the security of devices, and in particular on the vulnerability of devices to power analysis attacks are yet to be considered.This paper fills the gap and investigates how device aging can affect the susceptibility of a chip exposed to static power analysis attacks. To this end, we conduct both, simulation and practical experiments on real silicon. The experimental results are extracted from a realization of the PRESENT cipher fabricated using a 65nm commercial standard cell library. The results show that the amount of exploitable leakage through the static power consumption as a side channel is reduced when the device is aged. This can be considered as a positive development which can (even slightly) harden such static power analysis attacks. Additionally, this result is of great interest to static power side-channel adversaries since state-of-the-art leakage current measurements are conducted over long time periods under increased working temperatures and supply voltages to amplify the exploitable information, which certainly fuels aging-related device degradation.

scholarly journals CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design

2020 ◽  
pp. 121-146
Author(s):  
Jonas Krautter ◽  
Dennis Gnad ◽  
Mehdi Tahoori
Keyword(s):  
Power Distribution ◽  
Power Analysis ◽  
Process Variation ◽  
Physical Design ◽  
Design Parameters ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Power Analysis Attacks ◽  
Global And Local ◽  
The Impact

With virtualized Field Programmable Gate Arrays (FPGAs) on the verge of being deployed to the cloud computing domain, there is a rising interest in resolving recently identified security issues. Those issues result from different trusted and untrusted entities sharing the FPGA fabric and the Power Distribution Network. Researchers were able to perform both side-channel and fault attacks between logically isolated designs on the same FPGA fabric, compromising security of cryptographic modules and other critical implementations. Side-channel attacks specifically are enabled by the vast degree of freedom given to developers when making use of the basic FPGA resources. Both ring oscillators as well as long delay lines, implemented using low-level FPGA primitives, have been shown to provide sufficient data for simple or correlation-based power analysis attacks. In order to develop new or apply known countermeasures onto designs and implementations in a virtualized multi-tenant FPGA, we seek to fully understand the underlying mechanisms and dependencies of chip-internal side-channel attacks. Although the impact of process variation and other physical design parameters on side-channel vulnerability has been investigated in previous works, remote attacks between logically isolated partitions in multi-tenant FPGAs introduce new and unique challenges. Thus, we systematically analyze the impact of physical mapping of both attacker and victim design on the success of correlation power analysis attacks on the Advanced Encryption Standard (AES). We report our findings on a Xilinx Zynq 7000-based platform, which show that the effect of global and local placement as well as routing and process variation on the success of side-channel attacks almost exceeds the impact of hiding countermeasures. This result reveals fundamental challenges in secure virtualization of FPGAs, which have been mostly ignored so far. Eventually, our results may also help vendors and hypervisors in developing zero overhead side-channel countermeasures based on adequate global and local placement of isolated designs on a multi-tenant FPGA.

scholarly journals Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments

2019 ◽  
pp. 202-232
Author(s):  
Thorben Moos
Keyword(s):  
Field Effect Transistors ◽  
Low Noise ◽  
Operating Conditions ◽  
Side Channel ◽  
Clock Signal ◽  
Channel Measurements ◽  
Security Threat ◽  
Technology Scaling ◽  
Static Power ◽  
Technology Comparison

Semiconductor technology scaling faced tough engineering challenges while moving towards and beyond the deep sub-micron range. One of the most demanding issues, limiting the shrinkage process until the present day, is the difficulty to control the leakage currents in nanometer-scaled field-effect transistors. Previous articles have shown that this source of energy dissipation, at least in case of digital CMOS logic, can successfully be exploited as a side-channel to recover the secrets of cryptographic implementations. In this work, we present the first fair technology comparison with respect to static power side-channel measurements on real silicon and demonstrate that the effect of down-scaling on the potency of this security threat is huge. To this end, we designed two ASICs in sub-100nm CMOS nodes (90 nm, 65 nm) and got them fabricated by one of the leading foundries. Our experiments, which we performed at different operating conditions, show consistently that the ASIC technology with the smaller minimum feature size (65 nm) indeed exhibits substantially more informative leakages (factor of ~10) than the 90nm one, even though all targeted instances have been derived from identical RTL code. However, the contribution of this work extends well beyond a mere technology comparison. With respect to the real-world impact of static power attacks, we present the first realistic scenarios that allow to perform a static power side-channel analysis (including noise reduction) without requiring control over the clock signal of the target. Furthermore, as a follow-up to some proof-of-concept work indicating the vulnerability of masking schemes to static powerattacks, we perform a detailed study on how the reduction of the noise level in static leakage measurements affects the security provided by masked implementations. As a result of this study, we do not only find out that the threat for masking schemes is indeed real, but also that common leakage assessment techniques, such as the Welch’s t-test, together with essentially any moment-based analysis of the leakage traces, is simply not sufficient in low-noise contexts. In fact, we are able to show that either a conversion (resp. compression) of the leakage order or the recently proposed X2 test need to be considered in assessment and attack to avoid false negatives.

Impact of Turbine Center Frame Wakes on Downstream Rows in Heavy Duty Low Pressure Turbine

2019 ◽  
Author(s):  
Sara Biagiotti ◽  
Juri Bellucci ◽  
Michele Marconcini ◽  
Andrea Arnone ◽  
Gino Baldi ◽  
...  
Keyword(s):  
Experimental Data ◽  
Low Pressure ◽  
Forced Response ◽  
Point Of View ◽  
Operating Conditions ◽  
Response Analysis ◽  
Low Pressure Turbine ◽  
Harmonic Content ◽  
Partial Load ◽  
The Impact

Abstract In this work, the effects of Turbine Center Frame (TCF) wakes on the aeromechanical behavior of the downstream Low Pressure Turbine (LPT) blades are numerically investigated and compared with experimental data. A small industrial gas turbine has been selected as a test case, composed of a TCF followed by the two low pressure stages and a Turbine Rear Frame (TRF) before the exhaust plenum. Full annulus unsteady computations of the whole low-pressure module have been performed. Two operating conditions, full (100%) and partial (50%) load, have been investigated with the aim of highlighting the impact of TCF wakes convection and diffusion through the downstream rows. Attention was paid to the harmonic content of rotors’ blades. From an aerodynamic point of view, the results show a slower decay of the wakes through the downstream rows in off-design conditions as compared to the design point. The wakes generated by the struts at partial load persist throughout the domain outlet, while they are chopped and circumferentially transported by the rotors motion. This is due to the strong incidence variation at which the TCF works, which induces the growth of wide regions of separated flow on the rear part of the struts. Nevertheless, the analysis of the rotors’ frequency spectrum reveals that moving from design to off-design conditions, the effect of the TCF does not change significantly, thanks to the filtering action of the first LPT stage movable Nozzle Guide Vane (NGV). From unsteady calculations the harmonic contribution of all turbine components has been extracted, highlighting the effect of statoric parts on the last LPT blade. Anyhow the TCF harmonic content remains the most relevant from an aeromechanic point of view as per experimental evidence, and it is considered for a Forced Response Analysis (FRA) on the last LPT blade itself. Finally, aerodynamic and aeromechanic predictions have been compared with the experimental data to validate the numerical approach. In the last part of this paper some general design solutions, that can help mitigation of the TCF wakes impact, are discussed.

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks

2021 ◽  
Vol 26 (5) ◽  
pp. 1-36
Author(s):  
Darshana Jayasinghe ◽  
Aleksandar Ignjatovic ◽  
Roshan Ragel ◽  
Jude Angelo Ambrose ◽  
Sri Parameswaran
Keyword(s):  
Power Analysis ◽  
Fault Injection ◽  
Side Channel ◽  
Aging Effects ◽  
Side Channel Attacks ◽  
Power Analysis Attacks ◽  
Injection Attacks ◽  
Differential Fault Analysis ◽  
Secret Keys ◽  
Fault Injection Attacks

Side channel analysis attacks employ the emanated side channel information to deduce the secret keys from cryptographic implementations by analyzing the power traces during execution or scrutinizing faulty outputs. To be effective, a countermeasure must remove or conceal as many as possible side channels. However, many of the countermeasures against side channel attacks are applied independently. In this article, the authors present a novel countermeasure (referred to as QuadSeal ) against Power Analysis Attacks and Electromagentic Fault Injection Attacks (FIAs), which is an extension of the work proposed in Reference [27]. The proposed solution relies on algorithmically balancing both Hamming distances and Hamming weights (where the bit transitions on the registers and gates are balanced, and the total number of 1s and 0s are balanced) by the use of four identical circuits with differing inputs and modified SubByte tables. By randomly rotating the four encryptions, the system is protected against variations, path imbalances, and aging effects. After generating the ciphertext, the output of each circuit is compared against each other to detect any fault injections or to correct the faulty ciphertext to gain reliability. The proposed countermeasure allows components to be switched off to save power or to run four executions in parallel for high performance when resistance against power analysis attacks is not of high priority, which is not available with the existing countermeasures (except software based where source code can be changed). The proposed countermeasure is implemented for Advanced Encryption Standard (AES) and tested against Correlation Power Analysis and Mutual Information Attacks attacks (for up to a million traces), and none of the secret keys was found even after one million power traces (the unprotected AES circuit is vulnerable for power analysis attacks within 5,000 power traces). A detection circuit (referred to as C-FIA circuit) is operated using the algorithmic redundancy presented in four circuits of QuadSeal to mitigate Electromagnetic Fault Injection Attacks. Using Synopsys PrimeTime, we measured the power dissipation of QuadSeal registers and XOR gates to test the effectiveness of Quadruple balancing methodology. We tested the QuadSeal countermeasure with C-FIA circuit against Differential Fault Analysis Attacks up to one million traces; no bytes of the secret key were found. This is the smallest known circuit that is capable of withstanding power-based side channel attacks when electromagnetic injection attack resistance, process variations, path imbalances, and aging effects are considered.

scholarly journals Generalized Energy and Ecological Characteristics of the Process of Co-Firing Coal with Biomass in a Steam Boiler

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2634
Author(s):  
Joachim Kozioł ◽  
Joanna Czubala ◽  
Michał Kozioł ◽  
Piotr Ziembicki
Keyword(s):  
Structural Parameters ◽  
Point Of View ◽  
Operating Conditions ◽  
Hard Coal ◽  
Steam Boiler ◽  
Ecological Characteristics ◽  
Steam Boilers ◽  
Gross Energy ◽  
Harmful Substances ◽  
The Impact

One of the ways used to reduce the emission of carbon dioxide and other harmful substances is the implementation of biomass co-firing processes with coals. Such processes have been implemented for many years throughout many countries of the world, and have included using existing high-power coal boilers. Despite numerous experiments, there are still no analyses in the literature allowing for their generalization. The purpose of this paper is to determine the generalized energy and ecological characteristics of dust steam boilers co-firing hard coal with biomass. The energy characteristics determined in the paper are the dependence of the gross energy efficiency of boilers on such decision parameters as their efficiency and the share of biomass chemical energy in fuel. However, the ecological characteristics are the dependence of emission streams: CO, NOx, SO2, and dust on the same decision parameters. From a mathematical point of view, the characteristics are approximation functions between the efficiency values obtained from the measurements and the emission streams of the analysed harmful substances and the corresponding values of the decision parameters. Second-degree polynomials are assumed in this paper as approximation functions. Therefore, determining the characteristics came down to determining the constant coefficients occurring in these polynomials, the so-called structural parameters. The fit of the determined characteristics was assessed based on the coefficients of random variation and the test of estimated significance of structural parameters. Boiler characteristics can be used when forecasting the impact of changes in operating conditions on the effects achieved in existing, modernized, and designed boilers. The generalization of the characteristics was obtained from the measurement results presented in 10 independent sources used to determine them.

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