scholarly journals Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments

2019 ◽  
pp. 202-232
Author(s):  
Thorben Moos
Keyword(s):  
Field Effect Transistors ◽  
Low Noise ◽  
Operating Conditions ◽  
Side Channel ◽  
Clock Signal ◽  
Channel Measurements ◽  
Security Threat ◽  
Technology Scaling ◽  
Static Power ◽  
Technology Comparison

Semiconductor technology scaling faced tough engineering challenges while moving towards and beyond the deep sub-micron range. One of the most demanding issues, limiting the shrinkage process until the present day, is the difficulty to control the leakage currents in nanometer-scaled field-effect transistors. Previous articles have shown that this source of energy dissipation, at least in case of digital CMOS logic, can successfully be exploited as a side-channel to recover the secrets of cryptographic implementations. In this work, we present the first fair technology comparison with respect to static power side-channel measurements on real silicon and demonstrate that the effect of down-scaling on the potency of this security threat is huge. To this end, we designed two ASICs in sub-100nm CMOS nodes (90 nm, 65 nm) and got them fabricated by one of the leading foundries. Our experiments, which we performed at different operating conditions, show consistently that the ASIC technology with the smaller minimum feature size (65 nm) indeed exhibits substantially more informative leakages (factor of ~10) than the 90nm one, even though all targeted instances have been derived from identical RTL code. However, the contribution of this work extends well beyond a mere technology comparison. With respect to the real-world impact of static power attacks, we present the first realistic scenarios that allow to perform a static power side-channel analysis (including noise reduction) without requiring control over the clock signal of the target. Furthermore, as a follow-up to some proof-of-concept work indicating the vulnerability of masking schemes to static powerattacks, we perform a detailed study on how the reduction of the noise level in static leakage measurements affects the security provided by masked implementations. As a result of this study, we do not only find out that the threat for masking schemes is indeed real, but also that common leakage assessment techniques, such as the Welch’s t-test, together with essentially any moment-based analysis of the leakage traces, is simply not sufficient in low-noise contexts. In fact, we are able to show that either a conversion (resp. compression) of the leakage order or the recently proposed X2 test need to be considered in assessment and attack to avoid false negatives.

scholarly journals Exploring the Effect of Device Aging on Static Power Analysis Attacks

2019 ◽  
pp. 233-256
Author(s):  
Naghmeh Karimi ◽  
Thorben Moos ◽  
Amir Moradi
Keyword(s):  
Power Analysis ◽  
Point Of View ◽  
Operating Conditions ◽  
Positive Development ◽  
Side Channel ◽  
Power Analysis Attacks ◽  
Future Technology ◽  
Static Power ◽  
Device Aging ◽  
The Impact

Vulnerability of cryptographic devices to side-channel analysis attacks, and in particular power analysis attacks has been extensively studied in the recent years. Among them, static power analysis attacks have become relevant with moving towards smaller technology nodes for which the static power is comparable to the dynamic power of a chip, or even dominant in future technology generations. The magnitude of the static power of a chip depends on the physical characteristics of transistors (e.g., the dimensions) as well as operating conditions (e.g., the temperature) and the electrical specifications such as the threshold voltage. In fact, the electrical specifications of transistors deviate from their originally intended ones during device lifetime due to aging mechanisms. Although device aging has been extensively investigated from reliability point of view, the impact of aging on the security of devices, and in particular on the vulnerability of devices to power analysis attacks are yet to be considered.This paper fills the gap and investigates how device aging can affect the susceptibility of a chip exposed to static power analysis attacks. To this end, we conduct both, simulation and practical experiments on real silicon. The experimental results are extracted from a realization of the PRESENT cipher fabricated using a 65nm commercial standard cell library. The results show that the amount of exploitable leakage through the static power consumption as a side channel is reduced when the device is aged. This can be considered as a positive development which can (even slightly) harden such static power analysis attacks. Additionally, this result is of great interest to static power side-channel adversaries since state-of-the-art leakage current measurements are conducted over long time periods under increased working temperatures and supply voltages to amplify the exploitable information, which certainly fuels aging-related device degradation.

New Method to Determine the a-Si:H Pin Diode Series Resistance by Noise Measurements

1998 ◽  
Vol 507 ◽  
Author(s):  
F. Blecher ◽  
K. Seibel ◽  
M. Hillebrand ◽  
M. Böhm
Keyword(s):  
Series Resistance ◽  
Partial Information ◽  
Low Noise ◽  
Operating Conditions ◽  
New Method ◽  
Measuring System ◽  
Pin Diode ◽  
Noise Current ◽  
Current Voltage ◽  
Noise Measurements

ABSTRACTThe series resistance limits the linearity of photodiodes and decreases the efficiency of solar cells. It is usually determined from IV-measurements for moderate and high forward current density. This method, however, provides only partial information about Rs, since the series resistance depends on the operating point. An alternative method is based on noise measurements. System noise of the measuring system with a low-noise current-voltage converter has been investigated. A new method for extraction of photodiode series resistance from noise measurements is suggested. Noise measurements are carried out for a-Si:H pin diodes. The series resistance of an amorphous pin diode has been extracted for different operating conditions using the new measurement method.

Low Noise Junction Field Effect Transistors in a Silicon Radiation Detector Technology

2006 ◽  
Vol 53 (5) ◽  
pp. 3004-3012 ◽  
Author(s):  
G.-F. Dalla Betta ◽  
M. Boscardin ◽  
F. Fenotti ◽  
L. Pancheri ◽  
C. Piemonte ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Radiation Detector ◽  
Low Noise ◽  
Detector Technology ◽  
Junction Field Effect Transistors

Gain-ranging analog or digital seismic system

1974 ◽  
Vol 64 (1) ◽  
pp. 103-113 ◽  
Author(s):  
E. R. Kanasewich ◽  
W. P. Siewert ◽  
M. D. Burke ◽  
C. H. McCloughan ◽  
L. Ramsdell
Keyword(s):  
Dynamic Range ◽  
Wide Band ◽  
Low Noise ◽  
Active Filters ◽  
Operating Conditions ◽  
Natural Period ◽  
Analog System ◽  
Effective Dynamic ◽  
Different Levels ◽  
Seismic System

abstract A wide-band, gain-ranging amplifier is described that may be used for recording data with a dynamic range of 60 db in each of three different levels, 12 db apart, so that we achieve an “effective” dynamic ±160-v analog or 84-db digital, within a normal ±10-v analog system. As described, the ranging circuit reduces the gain of the amplifier by a factor of either 4 or 16 whenever the output signal approaches the maximum for the system. The wide-band response is achieved with low-noise operational amplifiers and second-order active filters. Signals with periods greater than 30 sec are amplified by 100 db and those with periods shorter than 1 sec are amplified by 70 db. The system works well in extending the useful output range of a Willmore Mark II seismometer with a natural period of 1.5 sec to over 40 sec under normal field operating conditions. When analog recording, the gain-range switching occurs when the input signal reaches ±8.1-v; when digital recording, the level is ±9.375 v. The period in a divide-by-4- or 16-state is preset by the experimentalist. The gain level is recorded on an extra channel which is also used to record absolute time.

Improving Gerotor Pump Performance Trough Design, Modeling and Simulation

2021 ◽  
Author(s):  
Lozica Ivanović ◽  
Miloš Matejić
Keyword(s):  
Low Noise ◽  
Operating Conditions ◽  
Design Parameters ◽  
Pump Efficiency ◽  
Hydraulic Systems ◽  
Wear Process ◽  
Gerotor Pump ◽  
Gerotor Pumps ◽  
Negative Effect ◽  
Compact Design

Gerotor pumps are well known by a compact design, simple structure and low noise level, which makes them suitable for use in the automotive industry, and especially in hydraulic systems for engine lubrication. One of the main disadvantages of gerotor pumps is the inability to adjust to wear, which significantly reduces the pump efficiency. In order to mitigate the negative effect of the inevitable wear process, this paper presents a methodology for determining the optimal combination of trochoid gears design parameters for a defined aspect. An appropriate mathematical model has been developed to analyze the effect of changes in gear design parameters in relation to maximum contact stresses, pressure changes in gerotor pump chambers and wear rate proportional factor (WRPF). Verification of the developed models was performed by realizing physical pairs of gears and laboratory experiments with simulation of pump operating conditions. The results and conclusions presented in this paper, with an emphasis on the actual work processes, bring very important perspectives for the gerotor pumps design with improved performance.

scholarly journals Single Event Effect Analysis of SiGe Low Noise Amplifier

2021 ◽  
Vol 25 (2) ◽  
pp. 57-64
Author(s):  
Manel Bouhouche ◽  
◽  
Saida Latreche ◽  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Low Noise ◽  
Operating Conditions ◽  
Low Noise Amplifier ◽  
Radiation Tolerance ◽  
Single Event ◽  
Effect Analysis ◽  
Sige Hbt ◽  
High Let ◽  
Noise Amplifier

This paper analyzes the single event transient (SET) response of low noise amplifier (LNA) designed using SiGe heterojunction bipolar transistors (HBT). To verify the radiation tolerance of the proposed LNA, a total of four cascode configurations were designed. Comprehensive mixed-mode simulations were performed to evaluate the SET susceptibility of considered LNA cascode configurations, and we have analyzed how the strike parameters affect their output response. In this fact the strike position, linear energy transfer (LET), and track radius, were varied, and the resulting transients were compared for the different LNA configurations. Through this study, the potential capability of the inverse mode SiGe heterojunction bipolar transistor (HBT) in LNA radiation tolerance was confirmed for various strike operating conditions. It has been demonstrated that the single event sensitivity was reduced for LNA employing inverse mode SiGe HBT for strike device. The strike influence on the different LNA configurations response depends on strike LET, where a reduced SET variation is observed for high LET.

scholarly journals Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 730 ◽  
Author(s):  
Shen-Li Chen ◽  
Pei-Lin Wu ◽  
Yu-Jen Chen
Keyword(s):  
High Voltage ◽  
Field Effect Transistors ◽  
Area Ratio ◽  
Operating Conditions ◽  
Elliptical Cylinder ◽  
Drift Region ◽  
Reference Device ◽  
Drain Side ◽  
Drain Region ◽  
Original Reference

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Rf Circuits ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Wireless Applications ◽  
Noise Amplifier ◽  
Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

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