scholarly journals Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes

2011 ◽  
pp. 102-107
Author(s):  
Manoj Kollam
Keyword(s):  
Code Generation ◽  
System Level ◽  
Practical Implementation ◽  
Direct Digital Synthesis ◽  
Synthesis Tool ◽  
Digital Synthesis ◽  
Selection For ◽  
Evaluation Board ◽  
Flexible Programming ◽  
Vhdl Code

This paper deals with the design & implementation of a Digital Modulator based on the FPGA. The design is implemented using the Enhanced Direct Digital Synthesis (DDS) Technology. The basic DDS architecture is enhanced with the minimum hardware to facilitate the complete system level support for different kinds of Modulations with minimal FPGA resources. The size of the ROM look up is reduced by using the mapping logic. The Design meets the present Software Define Radio (SDR) requirements and provides the user selection for desired modulation technique to be used. The VHDL programming language is used for modeling the hardware blocks for powerful and flexible programming and to avoid VHDL code generation tools. The design is simulated in the Model Sim Simulation Tool and Synthesized using the Xilinx ISE Synthesis Tool. The architecture is implemented on the SPARTAN-3A FPGA from Xilinx Family in the SPARTAN-3A evaluation board. The experimental results obtained demonstrate the usefulness of the proposed system in terms of the system resources, its capabilities for design, validation and practical implementation purposes.

scholarly journals Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec
Keyword(s):  
Code Generation ◽  
State Of The Art ◽  
Power Grids ◽  
Practical Implementation ◽  
System A ◽  
Measuring Devices ◽  
Point Representation ◽  
Measurement Algorithm ◽  
On Chip ◽  
Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

scholarly journals Piscivorous Bird Deterrent Device Based on a Direct Digital Synthesis of Acoustic Signals

2021 ◽  
Vol 27 (6) ◽  
pp. 42-48
Author(s):  
Arturs Aboltins ◽  
Dmitrijs Pikulins ◽  
Juris Grizans ◽  
Sergejs Tjukovs
Keyword(s):  
Acoustic Signals ◽  
Practical Implementation ◽  
Theoretical Base ◽  
Direct Digital Synthesis ◽  
Bird Songs ◽  
Design And Implementation ◽  
Digital Synthesis ◽  
Waveform Synthesis ◽  
Bird Call ◽  
The Given

This paper addresses the development of an acoustic deterrent device for the protection of fishponds and other objects against the unwanted presence of birds. The objective of the paper is not only providing of a deep analysis of available technologies for waveform synthesis and generation, but also building a theoretical base for the design and implementation of acoustic bird deterrent solutions. The paper addresses the synthesis of bird songs and calls using technologies for music, speech, and other types of acoustic signal processing. The second part of the paper is devoted to the unique algorithms and implementation details of the intelligent acoustic deterrence device prototype. The practical applicability of algorithms for bird call record conversion into synthesizer sequences has been analysed and possible issues are highlighted. The effectiveness and ease of practical implementation of the given method in the hardware are briefly discussed.

An Improved Doppler Shift Simulation Method Based on Third-Order DDS

2014 ◽  
Vol 614 ◽  
pp. 356-362 ◽  
Author(s):  
Rui Li ◽  
Yuan Long Cai ◽  
Xin Bei Bai ◽  
Ming Quan Lu
Keyword(s):  
Doppler Shift ◽  
Dynamic Range ◽  
Doppler Frequency ◽  
Simulation Method ◽  
Global Navigation Satellite Systems ◽  
Direct Digital Synthesis ◽  
Third Order ◽  
Satellite Systems ◽  
Digital Synthesis ◽  
Global Navigation Satellite

A method to simulate the Doppler frequency shift of high dynamic signals of Global Navigation Satellite Systems (GNSS) is provided in this paper. The methodology of the method based on third-order Direct Digital Synthesis (DDS) is introduced and the efficient implementation architecture is proposed. The design criteria of the DDS are investigated according to the precision and dynamic range of the Doppler shift. The simulation results are also demonstrated, which indicate that the method is available for the high precision Doppler shift simulation of GNSS signals.

Simulation of Stepped-Frequency LFM Radar Echo Based on FPGA

2012 ◽  
Vol 198-199 ◽  
pp. 948-953
Author(s):  
Jian Ping Ou ◽  
Sheng Qi Liu ◽  
Wei Niu
Keyword(s):  
Moving Target ◽  
Direct Digital Synthesis ◽  
Implementation Framework ◽  
Radar Echoes ◽  
Radar Echo ◽  
Digital Synthesis ◽  
Physical Simulations ◽  
Stepped Frequency ◽  
Logic Resource

An implementation framework of stepped-frequency LFM (SF-LFM) radar echoes simulator is presented in the paper based on the decomposition and calculation of SF-LFM radar echoes of a moving target. The proposed method can be implemented conveniently with direct digital synthesis (DDS) logic resource. The feasibility of this resolution is verified with computer and semi-physical simulations experiments.

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