scholarly journals Fault Tolerance in Carbon Nanotube Transistors Based Multi Valued Logic

2021 ◽  
Author(s):  
Gopalakrishnan Sundararajan
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Field Effect ◽  
Fault Tolerant ◽  
Field Effect Transistors ◽  
Transient Faults ◽  
Carbon Nanotube Transistors ◽  
Nanotube Transistors ◽  
Modular Redundancy ◽  
Carbon Nano Tube

This Chapter presents a solution for fault-tolerance in Multi-Valued Logic (MVL) circuits comprised of Carbon Nano-Tube Field Effect Transistors (CNTFET). This chapter reviews basic primitives of MVL and describes ternary implementations of CNTFET circuits. Finally, this chapter describes a method for error correction called Restorative Feedback (RFB). The RFB method is a variant of Triple-Modular Redundancy (TMR) that utilizes the fault masking capabilities of the Muller C element to provide added protection against noisy transient faults. Fault tolerant properties of Muller C element is discussed and error correction capability of RFB method is demonstrated in detail.

scholarly journals SOFTWARE IMPLEMENTED HARDWARE-TRANSIENT FAULTS DETECTION

2014 ◽  
pp. 26-30
Author(s):  
Goutam Kumar Saha
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Low Cost ◽  
Transient Faults ◽  
Fault Tolerant System ◽  
Cost Approach ◽  
Run Time ◽  
Commodity Systems ◽  
Fail Safe ◽  
Register Error

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.

A General Framework of Algorithm-Based Fault Tolerance Technique for Computing Systems

2014 ◽  
pp. 1-21 ◽  
Author(s):  
Hodjatollah Hamidi
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
General Framework ◽  
Fault Tolerant ◽  
Convolutional Code ◽  
Numerical Algorithms ◽  
Convolutional Codes ◽  
Computing Systems ◽  
Specific Level ◽  
Computing Paradigm

The Algorithm-Based Fault Tolerance (ABFT) approach transforms a system that does not tolerate a specific type of faults, called the fault-intolerant system, to a system that provides a specific level of fault tolerance, namely recovery. The ABFT philosophy leads directly to a model from which error correction can be developed. By employing an ABFT scheme with effective convolutional code, the design allows high throughput as well as high fault coverage. The ABFT techniques that detect errors rely on the comparison of parity values computed in two ways. The parallel processing of input parity values produce output parity values comparable with parity values regenerated from the original processed outputs and can apply convolutional codes for the redundancy. This method is a new approach to concurrent error correction in fault-tolerant computing systems. This chapter proposes a novel computing paradigm to provide fault tolerance for numerical algorithms. The authors also present, implement, and evaluate early detection in ABFT.

scholarly journals Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2074
Author(s):  
J.-Carlos Baraza-Calvo ◽  
Joaquín Gracia-Morán ◽  
Luis-J. Saiz-Adalid ◽  
Daniel Gil-Tomás ◽  
Pedro-J. Gil-Vicente
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Error Detection ◽  
Fault Injection ◽  
Error Correction Codes ◽  
Transient Faults ◽  
Tolerance Mechanism ◽  
Intermittent Faults ◽  
Risc Processor ◽  
Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

“Soft Error” Correction Method Based on Low Complexity Coding and Encoding Algorithm

2014 ◽  
Vol 556-562 ◽  
pp. 6344-6349
Author(s):  
Yan Kang Wei ◽  
Da Ming Wang ◽  
Wei Jia Cui
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Fault Tolerant ◽  
Low Complexity ◽  
Correction Method ◽  
Block Codes ◽  
Decoding Algorithms ◽  
Linear Block Codes ◽  
Data Errors ◽  
Linear Block

SEU is one of the major challenges affecting the reliability of computers on-board. In this paper, we design a kind of encoding and decoding algorithms with a low complexity based on the data correction method to resolve the data stream errors SEU may bring. Firstly, we use the theory of linear block codes to analyze various methods of data fault tolerance, and then from the encoding and decoding principle of linear block codes we design a kind of encoding and decoding algorithms with a low complexity of linear block code, The fault-tolerant coding method can effectively correct single-bit data errors caused by SEU, with low fault-tolerant overhead. Fault injection experiments show that: this method can effectively correct data errors caused by single event upset. Compared with other common error detection or correction methods, error correction performance of this method is superior, while its fault tolerance cost is less.

scholarly journals Demonstration of qubit operations below a rigorous fault tolerance threshold with gate set tomography

2017 ◽  
Vol 8 (1) ◽  
Author(s):  
Robin Blume-Kohout ◽  
John King Gamble ◽  
Erik Nielsen ◽  
Kenneth Rudinger ◽  
Jonathan Mizrahi ◽  
...  
Keyword(s):  
Quantum Information ◽  
Fault Tolerance ◽  
Error Correction ◽  
Error Rate ◽  
Fault Tolerant ◽  
Fast Algorithms ◽  
Quantum Error Correction ◽  
Qubit Operations ◽  
Quantum Error ◽  
Qubit Operation

Abstract Quantum information processors promise fast algorithms for problems inaccessible to classical computers. But since qubits are noisy and error-prone, they will depend on fault-tolerant quantum error correction (FTQEC) to compute reliably. Quantum error correction can protect against general noise if—and only if—the error in each physical qubit operation is smaller than a certain threshold. The threshold for general errors is quantified by their diamond norm. Until now, qubits have been assessed primarily by randomized benchmarking, which reports a different error rate that is not sensitive to all errors, and cannot be compared directly to diamond norm thresholds. Here we use gate set tomography to completely characterize operations on a trapped-Yb+-ion qubit and demonstrate with greater than 95% confidence that they satisfy a rigorous threshold for FTQEC (diamond norm ≤6.7 × 10−4).

Survey on Fault Tolerance Startgies for Advance Microelectronics Chip

2019 ◽  
Vol 7 (1) ◽  
pp. 01-04
Author(s):  
Himanshu Shekhar, Prof. Deepa Gianchandani
Keyword(s):  
Fault Tolerance ◽  
Power Supply ◽  
Fault Tolerant ◽  
Full Adder ◽  
Equipment Design ◽  
Transient Faults ◽  
Transient Fault

In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.

Fault Tolerant Magnetic Bearings

1999 ◽  
Vol 121 (3) ◽  
pp. 504-508 ◽  
Author(s):  
E. H. Maslen ◽  
C. K. Sortore ◽  
G. T. Gillies ◽  
R. D. Williams ◽  
S. J. Fedigan ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
High Speed ◽  
Fault Tolerant ◽  
High Capacity ◽  
Magnetic Bearing ◽  
Magnetic Bearings ◽  
Flexible Rotor ◽  
Variable Reluctance ◽  
Modular Redundancy ◽  
Bearing System

A fault tolerant magnetic bearing system was developed and demonstrated on a large flexible-rotor test rig. The bearing system comprises a high speed, fault tolerant digital controller, three high capacity radial magnetic bearings, one thrust bearing, conventional variable reluctance position sensors, and an array of commercial switching amplifiers. Controller fault tolerance is achieved through a very high speed voting mechanism which implements triple modular redundancy with a powered spare CPU, thereby permitting failure of up to three CPU modules without system failure. Amplifier/cabling/coil fault tolerance is achieved by using a separate power amplifier for each bearing coil and permitting amplifier reconfiguration by the controller upon detection of faults. This allows hot replacement of failed amplifiers without any system degradation and without providing any excess amplifier kVA capacity over the nominal system requirement. Implemented on a large (2440 mm in length) flexible rotor, the system shows excellent rejection of faults including the failure of three CPUs as well as failure of two adjacent amplifiers (or cabling) controlling an entire stator quadrant.

Providing fault tolerance through invasive computing

2016 ◽  
Vol 58 (6) ◽  
Author(s):  
Vahid Lari ◽  
Andreas Weichslgartner ◽  
Alexandru Tanase ◽  
Michael Witterauf ◽  
Faramarz Khosravi ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Parallel Applications ◽  
Technology Scaling ◽  
The Face ◽  
Tightly Coupled ◽  
On Chip ◽  
Modular Redundancy ◽  
Parallel Arrays ◽  
Selection Of

AbstractAs a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-Processor System-on-a-Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled Processor Arrays (). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

scholarly journals A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Mohsin Amin ◽  
Abbas Ramazani ◽  
Fabrice Monteiro ◽  
Camille Diou ◽  
Abbas Dandache
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
Error Control ◽  
Fault Tolerant ◽  
Error Rates ◽  
Main Memory ◽  
Transient Faults ◽  
Processor Core ◽  
Detection Techniques ◽  
Performance Area

We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.

Sign in / Sign up

Export Citation Format

Share Document