Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

2012 ◽  
Vol 51 (4S) ◽  
pp. 04DD12 ◽  
Author(s):  
Kousuke Miyaji ◽  
Chinglin Hung ◽  
Ken Takeuchi
Keyword(s):  
Flash Memory ◽  
Silicon On Insulator ◽  
Nand Flash ◽  
Bulk Silicon ◽  
Nand Flash Memory ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
20 Nm

Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory

2011 ◽  
Vol 32 (9) ◽  
pp. 1185-1187 ◽  
Author(s):  
Taehoon Kim ◽  
Nathan Franklin ◽  
Charan Srinivasan ◽  
Pranav Kalavade ◽  
Akira Goda
Keyword(s):  
Flash Memory ◽  
Scaling Behavior ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory

2014 ◽  
Vol 35 (1) ◽  
pp. 51-53 ◽  
Author(s):  
Kyunghwan Lee ◽  
Myounggon Kang ◽  
Seongjun Seo ◽  
Duckseoung Kang ◽  
Dong Hua Li ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Retention Characteristics ◽  
20 Nm

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

2015 ◽  
Vol 54 (4S) ◽  
pp. 04DD03 ◽  
Author(s):  
Duckseoung Kang ◽  
Kyunghwan Lee ◽  
Sangjin Kwon ◽  
Shinhyung Kim ◽  
Yuchul Hwang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
20 Nm

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

2014 ◽  
Vol 53 (4S) ◽  
pp. 04ED17
Author(s):  
Takeshi Sasaki ◽  
Masakazu Muraguchi ◽  
Moon-Sik Seo ◽  
Sung-kye Park ◽  
Tetsuo Endoh
Keyword(s):  
Flash Memory ◽  
Layer Structure ◽  
High Density ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
20 Nm ◽  
Memory Characteristics

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory

2014 ◽  
Author(s):  
Kyunghwan Lee ◽  
Duckseoung Kang ◽  
Hyungcheol Shin ◽  
Sangjin Kwon ◽  
Shinhyung Kim ◽  
...  
Keyword(s):  
Flash Memory ◽  
Failure Mechanisms ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
20 Nm

scholarly journals Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Yves Leduc ◽  
Emeric de Foucauld ◽  
Jerome Prouvee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Passive Component ◽  
Short Channel ◽  
Short Channel Effect ◽  
Back Gate ◽  
Fully Depleted ◽  
Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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