39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

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Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

Journal of Circuits System and Computers ◽

10.1142/s0218126621500730 ◽

2020 ◽

pp. 2150073 ◽

Cited By ~ 1

Author(s):

Ashish Sachdeva ◽

V. K. Tomar

Keyword(s):

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Static Random Access Memory ◽

Access Time ◽

Signal To Noise ◽

Access Memory ◽

Noise Margin ◽

Sram Cell ◽

Power Delay Product

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by [Formula: see text] as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than the considered D2p11T cell. The proposed 10T cell shows [Formula: see text] and [Formula: see text] narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by [Formula: see text] as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are [Formula: see text] and [Formula: see text] lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45[Formula: see text]nm technology file has been utilized to carry out simulations.

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Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0373 ◽

1998 ◽

Author(s):

Phil Schani ◽

S. Subramanian ◽

Vince Soorholtz ◽

Pat Liston ◽

Jamey Moss ◽

...

Keyword(s):

Electron Microscopy ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Temperature Sensitive ◽

Wafer Level ◽

Top Down ◽

Access Memory ◽

Transmission Electron ◽

Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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Challenges and Benefits of Product-Like SRAM in Technology Development

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0362 ◽

2011 ◽

Author(s):

Felix Beaudoin ◽

Stephen Lucarini ◽

Fred Towler ◽

Stephen Wu ◽

Zhigang Song ◽

...

Keyword(s):

Technology Development ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Development Phase ◽

High Complexity ◽

Access Memory ◽

Integration Schemes ◽

Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

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Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽

10.3390/electronics10121454 ◽

2021 ◽

Vol 10 (12) ◽

pp. 1454

Author(s):

Yoshihiro Sugiura ◽

Toru Tanzawa

Keyword(s):

Time Constant ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Memory Access ◽

Access Time ◽

Access Memory ◽

Delay Times ◽

Cell Current ◽

The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

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