Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FR15 ◽  
Author(s):  
Mariko Hayashi ◽  
Mitsuru Sometani ◽  
Tetsuo Hatakeyama ◽  
Hiroshi Yano ◽  
Shinsuke Harada
Keyword(s):  
Hole Trapping ◽  
Mos Devices ◽  
Capacitance Voltage

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Unified model of hole trapping, 1/f noise, and thermally stimulated current in MOS devices

2002 ◽  
Vol 49 (6) ◽  
pp. 2674-2683 ◽  
Author(s):  
D.M. Fleetwood ◽  
H.D. Xiong ◽  
Z.-Y. Lu ◽  
C.J. Nicklaw ◽  
J.A. Felix ◽  
...  
Keyword(s):  
Unified Model ◽  
Thermally Stimulated Current ◽  
Hole Trapping ◽  
Mos Devices

Hole Trapping in the NBTI Characteristic of SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 667-670
Author(s):  
Yan Jing He ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Meng Zhang ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Hole Trapping ◽  
Primary Mechanism ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
P Type

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

Characterization of Graphene Gate Electrodes for Metal-Oxide-Semiconductor Devices

MRS Advances ◽  
2017 ◽  
Vol 2 (02) ◽  
pp. 103-108 ◽  
Author(s):  
Yanbin An ◽  
Aniruddh Shekhawat ◽  
Ashkan Behnam ◽  
Eric Pop ◽  
Ant Ural
Keyword(s):  
Metal Oxide ◽  
High Frequency ◽  
Tunneling Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Heterogeneous Integration ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Capacitance Voltage

ABSTRACT We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.

Interface and Bulk Oxide Damage Induced by Boron Implantation

1985 ◽  
Vol 45 ◽  
Author(s):  
H. Wong ◽  
N.W. Cheung
Keyword(s):  
Tunneling Current ◽  
Electron Trapping ◽  
Constant Voltage ◽  
Hole Trapping ◽  
Capacitance Voltage ◽  
Boron Implantation ◽  
Thin Oxide ◽  
Oxide Damage

ABSTRACTInvestigations were carried out on the damage of SiO2 and the Si-SiO2 interface induced by boron implantation through polysilicon/SiO2 /p-Si structures with doses up to 1014cm−2 and annealed at 950°C. Using the constant voltage stressing technique, both capacitance-voltage and thin-oxide tunneling current measurements showed that both electron trapping and hole trapping are increased, and that ion-induced electron trapping overcompetes hole trapping for boron doses higher than 5×1013cm−2.

scholarly journals Analysis of Interface Charge Using Capacitance-Voltage Method for Ultra Thin HfO2 Gate Dielectric Based MOS Devices

2015 ◽  
Vol 57 ◽  
pp. 757-760 ◽  
Author(s):  
N.P. Maity ◽  
R.R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Gate Dielectric ◽  
Mos Devices ◽  
Interface Charge ◽  
Capacitance Voltage

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

2016 ◽  
Vol 858 ◽  
pp. 599-602 ◽  
Author(s):  
Yoshihito Katsu ◽  
Takuji Hosoi ◽  
Yuichiro Nanen ◽  
Tsunenobu Kimoto ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
High Stress ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Mos Capacitor ◽  
Hole Trapping ◽  
Uv Illumination ◽  
Mos Devices ◽  
Voltage Stress ◽  
Flatband Voltage

We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

Hole Trapping in SiC-MOS Devices Evaluated by Fast- CV Method

2017 ◽  
Author(s):  
M. Hayashi ◽  
M. Sometani ◽  
T. Hatakeyama ◽  
H. Yano ◽  
S. Harada
Keyword(s):  
Hole Trapping ◽  
Mos Devices
Sign in / Sign up

Export Citation Format

Share Document