scholarly journals Common Fallacies about Multivalued Circuits

2021 ◽  
pp. 67-83
Author(s):  
Daniel Etiemble
Keyword(s):  
Access Time ◽  
Combinational Circuits ◽  
Flash Memories ◽  
Quantum Devices ◽  
Trade Off ◽  
Chip Area ◽  
Fundamental Reason

For more than 60 years, many ternary or quaternary circuits have been proposed based on similar assumptions. We successively examine four of these assumptions and demonstrate that they are wrong. The fundamental reason for which m-valued combinational circuits are more complicated than the corresponding binary ones is explained. M-valued flash memories are used in USB devices because access times in not critical and a trade-off is possible between access time and chip area. If m-valued circuits are reduced to a very small niche in the binary world with semi-conductor technologies, there is a significant exception: quantum devices and computers are a true breakthrough as qbits are intrinsically multivalued. Successful m-valued circuits need m-valued devices as qbits.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Implementation of 4X4 Embedded Logic Memory for High Speed Applications

2017 ◽  
Vol 2 (4) ◽  
Author(s):  
Sudhanshu Janwadkar ◽  
Mahesh T. Kolte
Keyword(s):  
Power Consumption ◽  
Data Processing ◽  
High Speed ◽  
Propagation Delay ◽  
Memory Storage ◽  
Access Time ◽  
Complex Data ◽  
Flip Flop ◽  
Chip Area ◽  
Parallel Memory

With increasing complexity of data processing applications, there is a huge demand for high storage compact memories. It is highly desirable that memories have low access time and consume less power. Processing of data along with parallel memory storage has proved to be more efficient than serial operation. One such approach to paralleling processing is the concept of Embedded Memories. By inserting the logic within architecture of the flip-flop, the chip area can be reduced. Also, through means of Conditional Shut-down, the power consumption can be reduced. In this paper, we propose a modified dual dynamic hybrid node Embedded Logic D-Flip flop architecture. The work is based on DSCH 3.5 and Microwind 3.5 tools. We have simulated the design for 90nm, 65nm and 45nm technology respectively. Compared to the previous architectures, we have obtained a reduction in propagation delay by 15.38% and reduction in power consumption by 32.69%. Further, we have designed a 4X4 memory using our proposed Embedded Logic Flip Flop. The embedded memory finds applications in highly complex data processing applications, scan test circuits etc

A Sense Amplifier for Low Voltage Embedded Flash Memories

2014 ◽  
Vol 986-987 ◽  
pp. 1734-1737
Author(s):  
Hua Zhang
Keyword(s):  
Power Supply ◽  
Low Voltage ◽  
Power Supplies ◽  
Access Time ◽  
Flash Memories ◽  
Current Sensing ◽  
Sense Amplifier ◽  
Simulation Results ◽  
Embedded Flash

A sense amplifier applied for low voltage embedded flash memories is presented. The sense amplifier uses an enhanced current sensing method allowing power supplies lower than 1.5 V to be used. The sense amplifier was implemented in a FLASH realized with a 0.13 um FLASH technology. Simulation results showed a read access time of about 25 ns with a power supply of 1.5 V, and 32ns with a power supply of 1.2V.

scholarly journals High Speed FIR Filter Design using Multiplier Sharing and Sub-Expression Elimination Method

2019 ◽  
Vol 8 (4) ◽  
pp. 7414-7417
Keyword(s):  
High Speed ◽  
Simple Structure ◽  
Filter Design ◽  
Low Cost ◽  
Fir Filter ◽  
Access Time ◽  
Chip Area ◽  
Filter Order ◽  
The Cost ◽  
Fir Filter Design

FIR filter is the basic filter used in many DSP applications because of its linear phase , stability , low cost and simple structure . Designing a high- speed and hardware efficient FIR filter is a very difficult task as the complexity increases with the filter order .In most Application the higher order filters are required but the memory usage of filter increases exponentially with the order of the filter using multipliers occupy a large chip area and need more access time. So the design and implementation of highly efficient look up table (LUT) based circuit for the implementation using DA Algorithm increases the speed. Multiplier sharing and sub-expression elimination methods are proposed to optimize the Structural adders. These methods split the structural adders into smaller adder blocks to reduce the delay. In order to reduce the complexity of structural adders round-off can be performed at the cost of sacrificing precision of the filter.

A Flow-Preserving Algorithm for the Time-Cost Trade-Off Problem

1982 ◽  
Vol 14 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Suleyman Tufekci
Keyword(s):  
Time Cost ◽  
Trade Off

Dual Goals for Speed and Accuracy on the Same Performance Task

2012 ◽  
Vol 11 (3) ◽  
pp. 118-126 ◽  
Author(s):  
Olive Emil Wetter ◽  
Jürgen Wegge ◽  
Klaus Jonas ◽  
Klaus-Helmut Schmidt
Keyword(s):  
Memory Scanning ◽  
Performance Task ◽  
Performance Tasks ◽  
Trade Off ◽  
Test Experiment ◽  
Trade Offs ◽  
New Finding ◽  
Sternberg Paradigm ◽  
Speed Accuracy ◽  
Speed And Accuracy

In most work contexts, several performance goals coexist, and conflicts between them and trade-offs can occur. Our paper is the first to contrast a dual goal for speed and accuracy with a single goal for speed on the same task. The Sternberg paradigm (Experiment 1, n = 57) and the d2 test (Experiment 2, n = 19) were used as performance tasks. Speed measures and errors revealed in both experiments that dual as well as single goals increase performance by enhancing memory scanning. However, the single speed goal triggered a speed-accuracy trade-off, favoring speed over accuracy, whereas this was not the case with the dual goal. In difficult trials, dual goals slowed down scanning processes again so that errors could be prevented. This new finding is particularly relevant for security domains, where both aspects have to be managed simultaneously.

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