scholarly journals Finding out square root of an integer number using Single Electron Transistor

2021 ◽  
pp. 96-110
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
Power Consumption ◽  
Gate Voltage ◽  
Large Scale ◽  
Complementary Metal Oxide Semiconductor ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Integer Number ◽  
Single Electron Transistor ◽  
Square Root ◽  
Ultra Low Power

The single-electron transistor (SET) attracts the researchers, scientists or technologists to design and construct large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences in a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. The oscillatory conduction as the function of the variable-multiple /single gate voltage is exhibited by SET. This uncommon characteristic provides the ability of executing the functions of AND, OR, XOR, Inverter and some combinational circuits like multiplexer, subtractor etc. For implementing a square root circuit, SET would be a best candidate to fulfil the requirements. The processing speed of SET based devices will be nearly close to electronic speed. Noise during processing gets ultra-low when the circuits is built with SETs. The square root circuit is presented here for sixteen bit input numbers. The input bit numbers can be increased with the increasing of the depth of the pattern very easily. And this will provide us the greater accuracy about the squared root value. Power consumption in the single electron circuit is low irrespective of bipolar junction transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS) circuits. Reducing the numbers of nodes, the power consumption is reduced.

scholarly journals High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

2021 ◽  
Author(s):  
Mark Dong ◽  
Genevieve Clark ◽  
Andrew J. Leenheer ◽  
Matthew Zimmermann ◽  
Daniel Dominguez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Large Scale ◽  
Near Infrared ◽  
Response Times ◽  
Photonic Integrated Circuits ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Shifters ◽  
Oxide Semiconductor

AbstractRecent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

scholarly journals Measuring of an unknown voltage by using single electron transistor based voltmeter

2021 ◽  
Vol 24 (3) ◽  
pp. 277-287
Author(s):  
A.K. Biswas ◽  
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Noise ◽  
Single Electron ◽  
Single Electron Transistor ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Integration Density ◽  
Single Electron Device ◽  
Ultra Low Noise

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.

scholarly journals A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4462
Author(s):  
Malik Summair Asghar ◽  
Saad Arslan ◽  
HyungWon Kim
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Large Scale ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Input Image ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Spiking Neural Network ◽  
Digital Implementation

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Ultrasensitive broadband photodetectors based on two-dimensional Bi2O2Te films

2021 ◽  
Author(s):  
Pin Tian ◽  
Hongbo Wu ◽  
Libin Tang ◽  
Jinzhong Xiang ◽  
Rongbin Ji ◽  
...  
Keyword(s):  
Large Scale ◽  
2D Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Photocurrent Density ◽  
Short Wave ◽  
Oxide Semiconductor ◽  
Light Illumination ◽  
Two Dimensional ◽  
Weak Light

Abstract Two-dimensional (2D) materials exhibit many unique optical and electronic properties that are highly desirable for application in optoelectronics. Here, we report the study of photodetector based on 2D Bi2O2Te grown on n-Si substrate. The 2D Bi2O2Te material was transformed from sputtered Bi2Te3 ultrathin film after rapid annealing at 400 ℃ for 10 min in air atmosphere. The photodetector was capable of detecting a broad wavelength from 210 nm to 2.4 μm with excellent responsivity of up to 3x105 and 2x104 AW-1, and detectivity of 4x1015 and 2x1014 Jones at deep ultraviolet (UV) and short-wave infrared (SWIR) under weak light illumination, respectively. The effectiveness of 2D materials in weak light detection was investigated by analysis of the photocurrent density contribution. Importantly, the facile growth process with low annealing temperature would allow direct large-scale integration of the 2D Bi2O2Te materials with complementary metal-oxide–semiconductor (CMOS) technology.

scholarly journals Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Materials ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 2745 ◽  
Author(s):  
Luis Camuñas-Mesa ◽  
Bernabé Linares-Barranco ◽  
Teresa Serrano-Gotarredona
Keyword(s):  
Neural Networks ◽  
Learning Strategies ◽  
Large Scale ◽  
Sensory Information ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hardware Implementations ◽  
Learning Capabilities ◽  
Promising Solution

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

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