The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

Structural and electrical properties of ferroelectric BiFeO3/HfO2 gate stack for nonvolatile memory applications

Difficulties in the fabrication of direct interface of ferroelectric BiFeO3 on the gate of ferroelectric field effect transistor (FeFET) is well known. This paper reports the optimization and fabrication of ferroelectric/dielectric (BiFeO3/HfO[Formula: see text] gate stack for the FeFET applications. RF magnetron sputtering has been used for the deposition of BiFeO3, HfO2 films and their stack. X-Ray diffraction (XRD) analysis of BiFeO3 shows the dominant perovskite phase of (104), (110) orientation at 2[Formula: see text] at the annealing temperature of 500[Formula: see text]C. XRD analysis also confirms the amorphous nature of the HfO2 film at annealing temperature of 400[Formula: see text]C, 500[Formula: see text]C and 600[Formula: see text]C. Multiple angle analysis shows the variation ion the refractive index between 2.98–3.0214 for BiFeO3 and 2.74–2.9 for the HfO2 film with the annealing temperature. Metal/Ferroelectric/Silicon (MFS), Metal/Ferroelectric/Metal (MFM), Metal/Insulator/Silicon (MIS), and Metal/Ferroelectric/Insulator/Silicon (MFIS) structures have been fabricated to obtain the electric characteristic of the ferroelectric, dielectric and their stacks. Electrical characteristics of the MFIS structure show the memory improvement from 2.7[Formula: see text]V for MFS structure to 4.65[Formula: see text]V for MFIS structure with 8[Formula: see text]nm of buffer dielectric layer. This structure also shows the breakdown voltage of 40[Formula: see text]V with data retention capacity greater than [Formula: see text] iteration cycles.