Enabling the 2.5D Integration

2012 ◽  
Vol 2012 (1) ◽  
pp. 000254-000267 ◽  
Author(s):  
John Y. Xie ◽  
Hong Shi ◽  
Yuan Li ◽  
Zhe Li ◽  
Arif Rahman ◽  
...  

3D IC is the viable revolutionary technology that will enable system-level integration, miniaturization, optimal power management, increased data bandwidth, and eventually reduced system cost. Like any breakthrough technologies, it faces many challenges. Design methodology, integration technology, manufacturing process and new industrial ecosystem are the areas of focus. This paper will discuss these challenges and Altera's 3D integration development effort. 2.5D is an intermediate path to true 3D IC using silicon interposer and TSV (Through-Si-Via) stacking. The 2.5D stacking configuration offers different form factor, interconnect path, and thermal management options than monolithic packages, which could help to reduce system level power and thermal management pressure. It offers silicon level interconnect density, low inductive path and wide IO application. However, it's power delivery system (PDN) could be the bottleneck for the system to perform at the intended bandwidth and speed. Thus, the whole system, IC-Interposer-Package-PCB, must be considered holistically, and trade off study and compensation mechanism development are needed in such complex system level integration. There are many different 2.5D integration manufacturing flows currently under development. They can be categorized into two major flow options: Attaching interposer to substrate first, which can be called CoCoS (Chip on Chip on Substrate); or attaching device silicon to interposer first, which is also called CoWoS (Chip on Wafer on Substrate). The major challenges are in the areas of manufacturing process window and yield, thin wafer handling, testability and overall cost of the integration process. ,). This paper will discuss design consideration, manufacturability analysis, Logic/memory devices and silicon interposer interaction, and thermal management to enable the 2.5D integration. System level characterization and correlation with simulations are performed. The challenge of new supply-customer model and industrial ecosystem development associated with 2.5D integration will also be discussed.

Author(s):  
Stephen H. Pan ◽  
Norman Chang ◽  
Ji Zheng

Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology and its applications to accurately and efficiently predict power and temperature distribution for 3D ICs.


Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.


Author(s):  
Aleš Chvála ◽  
Robert Szobolovszký ◽  
Jaroslav Kováč ◽  
Martin Florovič ◽  
Juraj Marek ◽  
...  

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.


Sign in / Sign up

Export Citation Format

Share Document