scholarly journals Ultra-thin oxide breakdown for OTP development in power technologies

2020 ◽  
Author(s):  
Osvaldo Gasparri ◽  
Mirko Bernardoni ◽  
Paolo Del Croce ◽  
Andrea Baschirotto
Keyword(s):  
Oxide Layer ◽  
Applied Voltage ◽  
Performance Optimization ◽  
Oxide Thickness ◽  
Physical Models ◽  
Electrical Performance ◽  
Physical Analysis ◽  
Oxide Breakdown ◽  
Thin Oxide ◽  
Area Occupation

Abstract OTP (One Time Programmable) memory in power technology enables electrical performance optimization together with area occupation reduction. In this paper, the aspects relative to the oxide breakdown (which is the key mechanism for memory programmability) are studied and applied to the development of an antifuse OTP cell in a 350 nm-CMOS power technology. The physical analysis of the degradation phases of an oxide layer is presented together with the physical models, exploited to foresee the device time-to-breakdown depending on applied voltage, oxide thickness etc. The achieved results are used in the development and reliable implementation of OTP cells in the target 350 nm-CMOS node.

Correlation Between the Tunnelling Oxide and I-V Curves of MIS Photodiodes

2003 ◽  
Vol 762 ◽  
Author(s):  
H. Águas ◽  
L. Pereira ◽  
A. Goullet ◽  
R. Silva ◽  
E. Fortunato ◽  
...  
Keyword(s):  
Hydrogen Peroxide ◽  
Oxide Layer ◽  
Spectroscopic Ellipsometry ◽  
Chemical Deposition ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Signal To Noise ◽  
Rectification Factor ◽  
Mis Devices ◽  
The Ideal

AbstractIn this work we present results of a study performed on MIS diodes with the following structure: substrate (glass) / Cr (2000Å) / a-Si:H n+ (400Å) / a-Si:H i (5500Å) / oxide (0-40Å) / Au (100Å) to determine the influence of the oxide passivation layer grown by different techniques on the electrical performance of MIS devices. The results achieved show that the diodes with oxides grown using hydrogen peroxide present higher rectification factor (2×106)and signal to noise (S/N) ratio (1×107 at -1V) than the diodes with oxides obtained by the evaporation of SiO2, or by the chemical deposition of SiO2 by plasma of HMDSO (hexamethyldisiloxane), but in the case of deposited oxides, the breakdown voltage is higher, 30V instead of 3-10 V for grown oxides. The ideal oxide thickness, determined by spectroscopic ellipsometry, is dependent on the method used to grow the oxide layer and is in the range between 6 and 20 Å. The reason for this variation is related to the degree of compactation of the oxide produced, which is not relevant for applications of the diodes in the range of ± 1V, but is relevant when high breakdown voltages are required.

Further evidence for the presence of residual flaws in a thin oxide layer covering high purity aluminium

1993 ◽  
Vol 34 (12) ◽  
pp. 2099-2104 ◽  
Author(s):  
G.M. Brown ◽  
K. Shimizu ◽  
K. Kobayashi ◽  
G.E. Thompson ◽  
G.C. Wood
Keyword(s):  
Oxide Layer ◽  
High Purity ◽  
Thin Oxide Layer ◽  
Purity Aluminium ◽  
High Purity Aluminium ◽  
Thin Oxide

Effect of Electrolyte Concentration on Anodised Titanium in Mixture of β-Glycerophosphate (β-GP) and Calcium Acetate (CA)

2015 ◽  
Vol 1087 ◽  
pp. 116-120 ◽  
Author(s):  
Te Chuan Lee ◽  
Maizlinda Izwana Idris ◽  
Hasan Zuhudi Abdullah ◽  
Charles Christopher Sorrell
Keyword(s):  
Oxide Layer ◽  
Applied Voltage ◽  
Focused Ion Beam ◽  
Electrolyte Concentration ◽  
Ion Beam ◽  
Digital Camera ◽  
Disodium Salt ◽  
Calcium Acetate ◽  
Anode Surface ◽  
Ion Diffusion

Anodic oxidation is a surface modification method which combines electric field driven metal and oxygen ion diffusion for formation of oxide layer on the anode surface. Anodised titanium has been widely use in biomedical applications especially in dental implant. This study aimed to investigate the effect of electrolyte concentration on titanium. Specifically, the titanium foil was anodised in mixture of β-glycerophosphate disodium salt pentahydrate (β-GP) and calcium acetate monohydrate (CA) with different concentration (0.02 M + 0.2 M and 0.04 M + 0.4 M), anodising time (10 min), applied voltage (150, 200, 250, 300 and 350 V) and current density (10 mA.cm-2) at room temperature. Surface oxide properties of anodised titanium were characterised by using glancing angle X-ray diffraction (GAXRD), field emission scanning electron microscope (FESEM), focused ion beam (FIB) milling and digital camera. With increasing electrolyte concentration, the oxide layer became more porous. The GAXRD results also showed that rutile formed at high applied voltage (≥300 V) when the higher concentration of electrolyte was used.

Material Property of a Passive Oxide Formed on Alloy 600

2007 ◽  
Vol 26-28 ◽  
pp. 937-940 ◽  
Author(s):  
Dong Jin Kim ◽  
Hyuk Chul Kwon ◽  
Seong Sik Hwang ◽  
Hong Pyo Kim
Keyword(s):  
Corrosion Resistance ◽  
Oxide Layer ◽  
Passive Film ◽  
Electrochemical Impedance ◽  
Oxide Films ◽  
Oxide Thickness ◽  
Solution Temperature ◽  
Alloy 600 ◽  
Pressurized Water ◽  
Electrochemical Behaviors

Alloy 600 is used as a material for a steam generator tubing in pressurized water reactors(PWR) due to its high corrosion resistance under a PWR environment. In spite of its corrosion resistance, a stress corrosion cracking(SCC) has occurred on the primary side as well as the secondary side of a tubing. It is known that a SCC is related to the electrochemical behaviors of an anodic dissolution and a passivation of a bare surface of metals and alloys. Therefore in the present work, the passive oxide films on Alloy 600 have been investigated as a function of the solution temperature by using a potentiodynamic polarization, electrochemical impedance spectroscopy and a TEM, equipped with EDS. Moreover the semiconductive property was evaluated by using the Mott-Schottky relation. It was found that the passivity depends on the chemical composition and the densification of the oxide film rather than the oxide thickness. As the solution temperature of 0.5M H3BO3 increased, the thickness of the passive film increased but the oxide resistance of the passive film was decreased, indicating that the measured current in the passive region of the potentiodynamic curve is closely related to the stability of the passive film rather than the oxide thickness. It was found that the oxide films were composed of an outer oxide layer with a lower resistance and an inner oxide layer with a relatively higher resistance. From the Mott-Schottky relation, the oxide formed at 300oC showed a p-type semiconductor property unlike the n-type oxide films up to 250oC.

A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces

2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Thermal Oxidation ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Oxide Surface ◽  
Interface Morphology ◽  
Device Structure ◽  
Atomic Steps ◽  
Surface And Interface ◽  
Step Density

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

Effect of the Field Oxidation Process on the Electrical Characteristics of 6500V 4H-SiC JBS Diodes

2020 ◽  
Vol 1014 ◽  
pp. 144-148
Author(s):  
Ling Sang ◽  
Jing Hua Xia ◽  
Liang Tian ◽  
Fei Yang ◽  
Rui Jin ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Oxide Layer ◽  
Vapor Deposition ◽  
Oxidation Process ◽  
Chemical Vapor ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Field Plate ◽  
Plate Length ◽  
Field Oxide

The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

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