A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces

2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Thermal Oxidation ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Oxide Surface ◽  
Interface Morphology ◽  
Device Structure ◽  
Atomic Steps ◽  
Surface And Interface ◽  
Step Density

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

Investigation of Surface and Interface Morphology of Thermally Grown SiO2 Dielectrics on 4H-SiC(0001) Substrates

2011 ◽  
Vol 679-680 ◽  
pp. 342-345 ◽  
Author(s):  
Takuji Hosoi ◽  
Kohei Konzono ◽  
Yusuke Uenishi ◽  
Shuhei Mitani ◽  
Yuki Nakano ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Oxide Semiconductor ◽  
Oxide Surface ◽  
Initial Surface ◽  
Interface Morphology ◽  
Cross Sectional ◽  
Step Bunching ◽  
Surface And Interface ◽  
Transmission Electron ◽  
The Difference

Surface and interface morphology of thermal oxides grown on 4-off (0001) oriented 4H-SiC substrates by dry O2 oxidation was investigated using atomic force microscopy (AFM) and transmission electron microscopy (TEM). When step bunching was present on a starting wafer, oxide surface roughness was much larger than that of the starting 4H-SiC surface. This is attributed to the difference in oxidation rate between the terrace and the step face. A step-terrace structure on 4H-SiC(0001) was mostly preserved on the oxide surface, but pronounced oxidation occurred around the step bunching. Cross-sectional TEM observation showed that the SiO2/4H-SiC interface became smoother than the initial surface and the thickness of the SiO2 layer fluctuated. Such SiO2 thickness fluctuation may cause a local electric field concentration when a voltage was applied to the oxide, thus degrading the dielectric breakdown characteristics of 4H-SiC metal-oxide-semiconductor (MOS) devices.

Surface and Interfacial Topography of Oxides on Si(111) With Ultra-Low Atomic Step Density

1999 ◽  
Vol 592 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Initial Step ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Oxide Surface ◽  
Atomic Step ◽  
Layer By Layer ◽  
Initial Oxidation ◽  
Atomic Steps ◽  
Si Substrates ◽  
Step Density

ABSTRACTAtomic force microscopy has been used to study the morphology of the oxide surface and the Si-SiO2 interface after oxidation of Si(111) surfaces that are either totally free of atomic steps or have well characterized low step density. The step-free areas were formed by thermally processing a patterned Si surface in which flat areas are enclosed by a square array of ridges; flow of the atomic steps into the surrounding ridge barriers produces a regular array of step-free areas each of which can be up to ∼50µm×50µm. Arrays of widely spaced steps (e.g. 5µm) can also be produced in the step-free areas. AFM scans of the same areas were taken prior to (dry) oxidation, after oxidation, and after chemical removal of the oxide. It was found that at an oxide thickness in the 5-13nm range, the initial step structure of the underlying Si substrates is translated through the oxide to the surface after oxidation with the oxide surface being somewhat rougher than the initial substrate. Furthermore, the initial step morphology of the substrate remains at the Si-SiO2 interface after etching away the oxide by HF. The interface roughness is less than that of the oxide surface. The results suggest that the initial oxidation of silicon proceeds in a ‘layer by layer’ manner and not through a preferential step-flow oxide growth mode.

scholarly journals A Self-Consistent Model for Thermal Oxidation of Silicon at Low Oxide Thickness

2016 ◽  
Vol 2016 ◽  
pp. 1-13 ◽  
Author(s):  
Gerald Gerlach ◽  
Karl Maser
Keyword(s):  
Thermal Oxidation ◽  
Silicon Oxide ◽  
Surface Concentration ◽  
Oxide Thickness ◽  
Oxidation Time ◽  
Fickian Diffusion ◽  
Oxide Surface ◽  
Microelectronic Fabrication ◽  
Consistent Model ◽  
Self Consistent

Thermal oxidation of silicon belongs to the most decisive steps in microelectronic fabrication because it allows creating electrically insulating areas which enclose electrically conductive devices and device areas, respectively. Deal and Grove developed the first model (DG-model) for the thermal oxidation of silicon describing the oxide thickness versus oxidation time relationship with very good agreement for oxide thicknesses of more than 23 nm. Their approach named as general relationship is the basis of many similar investigations. However, measurement results show that the DG-model does not apply to very thin oxides in the range of a few nm. Additionally, it is inherently not self-consistent. The aim of this paper is to develop a self-consistent model that is based on the continuity equation instead of Fick’s law as the DG-model is. As literature data show, the relationship between silicon oxide thickness and oxidation time is governed—down to oxide thicknesses of just a few nm—by a power-of-time law. Given by the time-independent surface concentration of oxidants at the oxide surface, Fickian diffusion seems to be neglectable for oxidant migration. The oxidant flux has been revealed to be carried by non-Fickian flux processes depending on sites being able to lodge dopants (oxidants), the so-called DOCC-sites, as well as on the dopant jump rate.

Correlation Between the Tunnelling Oxide and I-V Curves of MIS Photodiodes

2003 ◽  
Vol 762 ◽  
Author(s):  
H. Águas ◽  
L. Pereira ◽  
A. Goullet ◽  
R. Silva ◽  
E. Fortunato ◽  
...  
Keyword(s):  
Hydrogen Peroxide ◽  
Oxide Layer ◽  
Spectroscopic Ellipsometry ◽  
Chemical Deposition ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Signal To Noise ◽  
Rectification Factor ◽  
Mis Devices ◽  
The Ideal

AbstractIn this work we present results of a study performed on MIS diodes with the following structure: substrate (glass) / Cr (2000Å) / a-Si:H n+ (400Å) / a-Si:H i (5500Å) / oxide (0-40Å) / Au (100Å) to determine the influence of the oxide passivation layer grown by different techniques on the electrical performance of MIS devices. The results achieved show that the diodes with oxides grown using hydrogen peroxide present higher rectification factor (2×106)and signal to noise (S/N) ratio (1×107 at -1V) than the diodes with oxides obtained by the evaporation of SiO2, or by the chemical deposition of SiO2 by plasma of HMDSO (hexamethyldisiloxane), but in the case of deposited oxides, the breakdown voltage is higher, 30V instead of 3-10 V for grown oxides. The ideal oxide thickness, determined by spectroscopic ellipsometry, is dependent on the method used to grow the oxide layer and is in the range between 6 and 20 Å. The reason for this variation is related to the degree of compactation of the oxide produced, which is not relevant for applications of the diodes in the range of ± 1V, but is relevant when high breakdown voltages are required.

scholarly journals Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Performance ◽  
Field Effect Transistors ◽  
Beryllium Oxide ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Effective Electron

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

scholarly journals Research on Performance Improvement of Photovoltaic Cells and Modules Based on Black Silicon

Crystals ◽  
2020 ◽  
Vol 10 (9) ◽  
pp. 753
Author(s):  
Zijian Chen ◽  
Haoyuan Jia ◽  
Yunfeng Zhang ◽  
Leilei Fan ◽  
Haina Zhu ◽  
...  
Keyword(s):  
Thermal Oxidation ◽  
Performance Improvement ◽  
Oxygen Flux ◽  
Electrical Performance ◽  
Black Silicon ◽  
Flux Control ◽  
Pv Module ◽  
Oxidation Step ◽  
Selection Of ◽  
Silicon Cell

This paper mainly studied the electrical performance improvement of black silicon photovoltaic (PV) cells and modules. The electrical performance of the cells and modules matched with black silicon was optimized through three different experiments. Firstly, in the pre-cleaning step, the effect of lotion selection on the cell performance was studied. Compared with alkaline lotion, using acidic lotion on black silicon wafer can achieve an efficiency improvement of the black silicon cell by nearly 0.154%. Secondly, the influence of oxygen flux control of the thermal oxidation step on the improvement of cell efficiency was studied. The addition of the thermal oxidation step and its oxygen flux control resulted in an efficiency increase of the black silicon cell of nearly 0.11%. The most optimized volume control of the oxygen flux is at 2200 standard cubic centimeter per minute (SCCM). Finally, in the module packaging process, the selection of components will also greatly affect the performance of the black silicon PV module. The most reasonable selection of components can increase the output power of the black silicon PV module by 6.13 W. In a word, the technical indication of the electrical performance improvement suggested in this study plays an important guiding role in the actual production process.

scholarly journals Graphene-Based Contacts for Optoelectronic Devices

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 919
Author(s):  
Susana Fernández ◽  
Antonio Molinero ◽  
David Sanz ◽  
José González ◽  
Marina Cruz ◽  
...  
Keyword(s):  
Optoelectronic Devices ◽  
Transparent Conductive Oxide ◽  
Future Generation ◽  
Electrical Performance ◽  
Commercial Application ◽  
Graphene Monolayer ◽  
Metal Contacts ◽  
Device Structure ◽  
Ultrasonic Bonding ◽  
Near Future

Hybrid transparent contacts based on combinations of a transparent conductive oxide and a few graphene monolayers were developed in order to evaluate their optical and electrical performance with the main aim to use them as front contacts in optoelectronic devices. The assessment of the most suitable strategies for their fabrication was performed by testing different protocols addressing such issues as the protection of the device structure underneath, the limitation of sample temperature during the graphene-monolayer transfer process and the determination of the most suitable stacking structure. Suitable metal ohmic electrodes were also evaluated. Among a number of options tested, the metal contact based on Ti + Ag showed the highest reproducibility and the lowest contact resistivity. Finally, with the objective of extracting the current generated from optoelectronic devices to the output pins of an external package, focusing on a near future commercial application, the electrical properties of the connections made with an ultrasonic bonding machine (sonic welding) between the optimized Ti + Ag metal contacts and Al or Au micro-wires were also evaluated. All these results have an enormous potential as hybrid electrodes based on graphene to be used in novel designs of a future generation of optoelectronic devices, such as solar cells.

Sign in / Sign up

Export Citation Format

Share Document