High reliability silver paste for die bonding

1989 ◽  
Vol 20 (3) ◽  
pp. 50
Author(s):  
Y. Okabe ◽  
A. Kusuhara ◽  
M. Mizuno ◽  
K. Horiuchi

2010 ◽  
Vol 2010 (1) ◽  
pp. 000474-000478 ◽  
Author(s):  
David J Rasmussen ◽  
Rodney Thompson

Whether the need is due to poorly bondable materials, non-flat bonding surfaces, odd packaging situations, or just the need for high reliability; the integrity of a wire bond interconnect can usually be greatly improved through the proper use of Auxiliary Wires. Auxiliary Wires are defined as Security Wires, Security Bumps, or Stand-Off Stitch (aka Stitch on Bump). The old stand-by Security Wire has been an asset for several decades, however, this is being replaced by Security Bumps which require a smaller second bond termination area. Further, Stand-Off Stitch (SOS) has many more applications and also has many side benefits that could be incorporated into a circuit design for better wire strength properties, fewer interconnects (die to die bonding), and lower loops. Stand-Off Stitch bonding involves the placement of a ball bump at one end of the wire interconnect, then placing a wire with another ball at the other end of the interconnect and stitching off the wire on the previous placed ball bump. This results in a near homogeneous stitch bond interconnect to the bump with an inherent improvement in stitch bond pull strength. Another use for SOS is Reverse Bonding (Stitch bond on bump on die bond pad) often resulting in a lower loop profile than standard forward wire loop and the loop is stronger because the wire hasn't been work annealed above the ball (in the Heat Affected Zone). A major impediment to the implementation of SOS is the retraining of visual inspectors and the approval of quality departments.


Author(s):  
Kisho Ashida ◽  
Kenya Kawano ◽  
Naotaka Tanaka ◽  
Atsushi Nishikizawa ◽  
Nobuya Koike

Evaluating silver paste strength for die bonding during the reflow soldering process is important, as silver paste fracturing is one of the main causes of package failure. First, we assumed that the fracturing was caused by thermal stress and vapor pressure at the interface between the resin and the copper lead frame. Next, we measured the silver paste fracture strength using a three-point bending test and a bonded specimen with silver paste. Finally, we predicted the occurrence of silver paste fracturing by calculating the silver paste stress during reflow soldering process and comparing it with the measured fracture strength. Results obtained in strength evaluation analysis were consistent with those obtained in package reflow tests, indicating that this method can be used to predict the occurrence of silver paste fracturing.


1981 ◽  
Vol 8 (1-2) ◽  
pp. 103-109 ◽  
Author(s):  
N. Miura ◽  
Y. Fuura ◽  
K. Uchida

The Substrate Carrier System (S. C. System) is a new manufacturing technique for small size hybrid IC with IMST (Insulated Metal Substrate Technology)substrate which is used for power hybrid IC (STK series). The point of this system is to treat both substrate process and assembly process in the manufacturing process of hybrid IC, with several IC substrates at the same time. In the printing process, multi-IC pattern are made on a large IMST substrate at the same time and the substrate after completion of printing process are slit-punched to have the frame configuration where individual IC substrates are conected by tie-bar. Moreover in the assembly process which involves die-bonding and wire-bonding, the substrate is carried by the pitch of IC substrate, utilizing the frame construction, which can provide the automatic processes.This Substrate Carrier System is applied to many kinds of hybrid IC for low-frequency applications as a system of high reliability and productivity.


Author(s):  
Naoaki Tsurumi ◽  
Noriyuki Masago ◽  
Taiki Baba ◽  
Hiroyuki Murata ◽  
Yuta Tsuji ◽  
...  

2018 ◽  
Vol 140 ◽  
pp. 64-72 ◽  
Author(s):  
Jie Li ◽  
Xin Li ◽  
Lei Wang ◽  
Yun-Hui Mei ◽  
Guo-Quan Lu

2007 ◽  
Vol 353-358 ◽  
pp. 2948-2953 ◽  
Author(s):  
Thomas G. Lei ◽  
Jesus Calata ◽  
Shu Fang Luo ◽  
Guo Quan Lu ◽  
Xu Chen

Today, reflow soldering is a commonly used technique to establish large-area joints in power electronics modules. These joints are needed to attach large-area (>1 cm2) power semiconductor chips to the substrate, e.g., a direct-bond copper substrate, and the multichip module substrate to a copper base plate for heat spreading. Thermal performance, specifically thermal conductivity and thermomechanical reliability, of these large-area joints are critical to the electrical performance and lifetime of the power modules. Soft solder alloys, including the lead-tin eutectic and lead-free alternatives, have low thermal conductivities and are highly susceptible to fatigue failure. As demands mount for higher power density, higher junction temperature, and longer lifetime out of the power modules, reliance on solder-based joining is becoming a barrier for further advancement in power electronics systems. Recently, we successfully demonstrated lowtemperature sintering of nanoscale silver paste as a lead-free solution for achieving highperformance, high-reliability, and high-temperature interconnection of small devices (<0.09 cm2). In this paper, we report the results of our study to extend the low-temperature sintering technique to large-area joints. The study involved redesigning the organic and inorganic components of the nanoscale silver paste, analyzing the burnout kinetics of the various organic species sandwiched between large-area plates, and developing desirable temperature-time profile to improve sintering and bonding strength of the joints.


Author(s):  
John R. Devaney

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.


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