Low-Temperature Sintering of Nanoscale Silver Paste for Large-Area Joints in Power Electronics Modules

2007 ◽  
Vol 353-358 ◽  
pp. 2948-2953 ◽  
Author(s):  
Thomas G. Lei ◽  
Jesus Calata ◽  
Shu Fang Luo ◽  
Guo Quan Lu ◽  
Xu Chen
Keyword(s):  
Low Temperature ◽  
Power Electronics ◽  
High Reliability ◽  
Copper Substrate ◽  
Lead Free ◽  
Electrical Performance ◽  
Low Temperature Sintering ◽  
Large Area ◽  
Silver Paste ◽  
Power Modules

Today, reflow soldering is a commonly used technique to establish large-area joints in power electronics modules. These joints are needed to attach large-area (>1 cm2) power semiconductor chips to the substrate, e.g., a direct-bond copper substrate, and the multichip module substrate to a copper base plate for heat spreading. Thermal performance, specifically thermal conductivity and thermomechanical reliability, of these large-area joints are critical to the electrical performance and lifetime of the power modules. Soft solder alloys, including the lead-tin eutectic and lead-free alternatives, have low thermal conductivities and are highly susceptible to fatigue failure. As demands mount for higher power density, higher junction temperature, and longer lifetime out of the power modules, reliance on solder-based joining is becoming a barrier for further advancement in power electronics systems. Recently, we successfully demonstrated lowtemperature sintering of nanoscale silver paste as a lead-free solution for achieving highperformance, high-reliability, and high-temperature interconnection of small devices (<0.09 cm2). In this paper, we report the results of our study to extend the low-temperature sintering technique to large-area joints. The study involved redesigning the organic and inorganic components of the nanoscale silver paste, analyzing the burnout kinetics of the various organic species sandwiched between large-area plates, and developing desirable temperature-time profile to improve sintering and bonding strength of the joints.

Embedded Die Packages and Modules for Power Electronics Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001918-001947 ◽  
Author(s):  
Lars Boettcher ◽  
S. Karaszkiewicz ◽  
D. Manessis ◽  
A. Ostmann
Keyword(s):  
Power Electronics ◽  
Power Efficiency ◽  
High Reliability ◽  
Heat Removal ◽  
Testing Temperature ◽  
Temperature Cycling ◽  
Switching Frequency ◽  
Large Area ◽  
Power Modules ◽  
Embedded Power

Packages and modules with embedded semiconductor dies are of interest for various application fields and power classes. First packages in the lower power range are available in volume production since almost six years. Recent developments focus on medium and higher power applications raging over 500W into the kW range. Different approaches are available to realize such packages and modules. This paper will give an overview and detailed description of the latest approaches for such embedded die structures. In common of all of these approaches, is the use of laminate based die embedding, which uses standard PCB manufacturing technologies. Main differences are the used base substrate, which can still be a ceramic (DBC), Cu leadframe or high current substrate. Examples for the different methods will be given. As the main part, this paper will describe concepts, which enable significant smaller form-factor of power electronics modules, thereby allowing for lower price, high reliability, capability of direct mounting on e.g. a motor so as to form one unit with the motor housing, wide switching frequency range (for large application field) and high power efficiency. The innovative character of this packaging concept is the idea to embed the power drive components (IGBTs, MOSFETs, diode) as thinned chips into epoxy-resin layer built-up and to realize large-area interconnections on both sides by direct copper plating the dies to form a conductor structure with lowest possible electrical impedance and to achieve an optimum heat removal. In this way a thin core is formed on a large panel format which is called Embedded Power Core. The paper will specifically highlight the first results on manufacturing an embedded power discrete package as an example of an embedded power core containing a thin rectifier diode. For module realization, the power cores are interconnected to insulated metal substrates (IMS) by the use of Ag sintering interconnection technologies for the final manufacturing of Power modules. The paper will elaborate on the sintering process for Power Core/IMS interconnections, the microscopically features of the sintered interfaces, and the lateral filling of the sintering gap with epoxy prepregs. Firstly, 500W power modules were manufactured using this approach. Reliability testing results, solder reflow testing, temperature cycling test and active power cycling, will be discussed in detail.

Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area $({>}100~{\rm mm}^{2})$ Chips

2010 ◽  
Vol 33 (1) ◽  
pp. 98-104 ◽  
Author(s):  
Thomas Guangyin Lei ◽  
Jesus Noel Calata ◽  
Guo-Quan Lu ◽  
Xu Chen ◽  
Shufang Luo
Keyword(s):  
Low Temperature ◽  
Low Temperature Sintering ◽  
Large Area ◽  
Silver Paste

Low temperature low pressure solid-state porous Ag bonding for large area and its high-reliability design in die-attached power modules

2019 ◽  
Vol 45 (7) ◽  
pp. 9573-9579 ◽  
Author(s):  
Chuantong Chen ◽  
Dongjin Kim ◽  
Zhenghong Wang ◽  
Zheng Zhang ◽  
Yue Gao ◽  
...  
Keyword(s):  
Solid State ◽  
Low Temperature ◽  
High Reliability ◽  
Low Pressure ◽  
Large Area ◽  
Reliability Design ◽  
Power Modules

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

Low-Temperature Joining Technique as Interconnection Technology for Power Electronics

2011 ◽  
Vol 324 ◽  
pp. 437-440
Author(s):  
Raed Amro
Keyword(s):  
Low Temperature ◽  
Power Electronics ◽  
Life Time ◽  
Junction Temperature ◽  
Limiting Factors ◽  
Power Devices ◽  
Packaging Technology ◽  
Power Cycling ◽  
Power Modules ◽  
Bond Wires

There is a demand for higher junction temperatures in power devices, but the existing packaging technology is limiting the power cycling capability if the junction temperature is increased. Limiting factors are solder interconnections and bond wires. With Replacing the chip-substrate soldering by low temperature joining technique, the power cycling capability of power modules can be increased widely. Replacing also the bond wires and using a double-sided low temperature joining technique, a further significant increase in the life-time of power devices is achieved.

Performance Assessment of a Low Temperature Polymer Conductor for Lead-Free Soldering Processes

2014 ◽  
Vol 2014 (1) ◽  
pp. 000251-000257
Author(s):  
Steven Grabey ◽  
Samson Shahbazi ◽  
Sarah Groman ◽  
Catherine Munoz
Keyword(s):  
Low Temperature ◽  
Thick Film ◽  
Elevated Temperatures ◽  
Printed Electronics ◽  
High Reliability ◽  
Sem Analysis ◽  
Lead Free ◽  
Sac305 Solder ◽  
Soldering Process ◽  
Lead Free Solders

An increased interest in low temperature polymer thick film products has become apparent due to the rise of the printed electronics market. The specifications for these products are becoming more demanding with expectations that the low temperature products should perform at a level that is typically reserved for their high temperature counterparts; including solderability with lead free solders, high reliability and strong adhesion. Traditionally, it has only been possible to use leaded solders for soldering to polymer based thick film conductors. Over the last 15 years environmental concerns and legislation have pushed the industry towards a lead free approach. The shift to lead free solders, while beneficial, provides new challenges during processing. The high temperatures required for a lead-free soldering process yield a naturally harsher environment for polymer thick film pastes. In the past these conditions have proven too harsh for the pastes to survive. The polymer thick film discussed in this document aims to address some of these concerns for a highly reliable and easy to process polymer thick film paste. Due to the poor leaching characteristics of polymer thick films, at elevated temperatures, the predecessors of this paste typically soldered at low temperatures with leaded solders. The goal of this paper is to present a low temperature paste that is compatible with a variety of substrates and readily accepts lead-free solder. This paper will discuss a newly formulated low temperature curing (150°C – 200°C) RoHS and REACH compliant paste that shows excellent solderability with SAC305 solder. The paste was evaluated using a dip soldering method at 235°C–250°C on a variety of substrates. The data presented includes solder acceptance, adhesion data, thermal analysis and SEM analysis.

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