Synergetic effects of monoethanolamine (MEA) and post-deposition calcination on biosynthesized CeO2 nanostructures spin-coated on silicon substrate

2021 ◽  
pp. 125656
Author(s):  
Saad Milad Ali Nsar ◽  
Zainuriah Hassan ◽  
Kuan Yew Cheong ◽  
Way Foong Lim
Keyword(s):  
Silicon Substrate ◽  
Synergetic Effects ◽  
Post Deposition

Formation of Cylindrical Nanoholes in Heavily Doped P-Type Si(100) Substrate via Pt Nanoparticles-Assisted Chemical Etching

2012 ◽  
Vol 535-537 ◽  
pp. 362-367 ◽  
Author(s):  
Bao Zhu ◽  
Lian Jie Li ◽  
Qing Qing Sun ◽  
Hong Liang Lu ◽  
Shi Jin Ding ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Chemical Etching ◽  
Early Stage ◽  
Pt Nanoparticles ◽  
High Concentration ◽  
Post Deposition Annealing ◽  
Heavily Doped ◽  
Underlying Mechanisms ◽  
P Type ◽  
Post Deposition

Metal assisted chemical etching of heavily doped p-type Si(100) wafer was investigated in a solution containing HF and hydrogen peroxide using Pt nanoparticles as catalyst. The Pt nanoparticles were formed on Si(100) substrate by magnetron sputtering and post-deposition annealing. In a solution containing low concentration HF, formation of cylindrical nanoholes are unstable in the early stage of the etching process. After that, nanoholes with diameters ranging from 40 to 50 nm are stably formed in silicon substrate and the calculated growing rate is 60 nm/min. Instead, in a solution containing high concentration HF, cylindrical nanoholes with a diameter of about 10 nm can be stably produced in silicon substrate all the time and the growing rate is increased to as fast as 160 nm/min. In both cases, no Pt nanoparticles are observed at the bottom of the nanoholes. Finally, the underlying mechanisms of the aforementioned phenomena are also discussed.

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

Transport Properties Of Metallic Nanowires On Silicon Substrate

2014 ◽  
Vol 2 (1) ◽  
pp. 20-23
Author(s):  
Jaskiran Kaur ◽  
◽  
Surinder Singh ◽  
Keyword(s):  
Transport Properties ◽  
Silicon Substrate ◽  
Metallic Nanowires

Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Silicon Substrate ◽  
Processing Technique ◽  
Electrical Characteristics ◽  
Localization Method ◽  
The Right ◽  
Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

Studies on a Novel Qualification Method of Silicon Nitride Layer

2016 ◽  
Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Silicon Substrate ◽  
Nitride Layer ◽  
Passivation Layer ◽  
Wafer Fabrication ◽  
Wafer Surface ◽  
Si3n4 Layer ◽  
Silicon Nitride Layer ◽  
Passivation Layers ◽  
Pinhole Test

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

Sign in / Sign up

Export Citation Format

Share Document