WITHDRAWN: Visualization of gate-bias dependent carrier distribution in SiC power-MOSFET using super-higher-order scanning nonlinear dielectric microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Higher Order ◽  
Gate Bias ◽  
Carrier Distribution ◽  
Power Mosfet ◽  
Nonlinear Dielectric

Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Cross Section ◽  
Measurement System ◽  
Higher Order ◽  
Depletion Layer ◽  
Gate Bias ◽  
Power Mosfet ◽  
Nonlinear Dielectric ◽  
Voltage Dependent ◽  
Carrier Redistribution ◽  
Source Voltage

Abstract Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.

Evaluation of Power SiC-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy—Imaging of Carrier Distribution and Depletion Layer

2014 ◽  
Author(s):  
N. Chinone ◽  
Y. Cho ◽  
T. Nakamura
Keyword(s):  
Semiconductor Device ◽  
Low Cost ◽  
Semiconductor Devices ◽  
Higher Order ◽  
Depletion Layer ◽  
Dopant Distribution ◽  
Carrier Distribution ◽  
Microscopy Imaging ◽  
Nonlinear Dielectric ◽  
Power Semiconductor

Abstract Evaluation techniques for semiconductor devices are keys for device development with low cost and short time to market. Especially, dopant and depletion layer distribution in devices is a critical electrical property that needs to be evaluated. Super-higher-order nonlinear dielectric microscopy (SHOSNDM) is one of the promising techniques for semiconductor device evaluation. We developed a method for imaging detailed dopant distribution and depletion layers in semiconductor devices using SHO-SNDM. As a demonstration, a cross-section of a SiC power semiconductor device was measured by this method and detailed dopant distribution and depletion layer distributions were imaged.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Two-Dimensional Local Deep-Level Transient Spectroscopy Imaging Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2016 ◽  
Author(s):  
N. Chinone ◽  
Y. Cho ◽  
R. Kosugi ◽  
Y. Tanaka ◽  
S. Harada ◽  
...  
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Higher Order ◽  
Trap Density ◽  
New Technique ◽  
Two Dimensional ◽  
Nonlinear Dielectric ◽  
Annealing Conditions ◽  
Transient Spectroscopy ◽  
A New Technique

Abstract A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique. SiCVSiC structure samples with different post oxidation annealing conditions were measured. We observed that the local DLTS signal decreases with post oxidation annealing (POA), which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiCVSiC interface.

Higher Order Nonlinear Dielectric Microscopy

2001 ◽  
Vol 688 ◽  
Author(s):  
Yasuo Cho ◽  
Koya Ohara
Keyword(s):  
Depth Resolution ◽  
Higher Order ◽  
Ferroelectric Materials ◽  
Unit Cell ◽  
Dielectric Constants ◽  
Surface Layers ◽  
Nonlinear Dielectric ◽  
Microscopy Technique ◽  
Cell Thickness

AbstractA higher order nonlinear dielectric microscopy technique with higher lateral and depth resolution than conventional nonlinear dielectric imaging is investigated. The proposed technique involves the measurement of higher order nonlinear dielectric constants, with a depth resolution of down to 1.5 nm. The technique is demonstrated to be very useful for observing surface layers of the order of unit cell thickness on ferroelectric materials.

New Functions of Scanning Nonlinear Dielectric Microscopy –Higher-Order Measurement and Vertical Resolution–

2001 ◽  
Vol 40 (Part 1, No. 5B) ◽  
pp. 3544-3548 ◽  
Author(s):  
Yasuo Cho ◽  
Koya Ohara ◽  
Atsushi Koike ◽  
Hiroyuki Odagawa
Keyword(s):  
Higher Order ◽  
Vertical Resolution ◽  
Nonlinear Dielectric

The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

2014 ◽  
Vol 598 ◽  
pp. 361-364 ◽  
Author(s):  
Chih Chieh Hsu ◽  
Chien Hsun Wu
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Oxide Thin Film ◽  
High Electron ◽  
Indium Gallium Zinc Oxide ◽  
Gate Bias ◽  
Carrier Distribution ◽  
Fully Depleted ◽  
Gate Capacitance

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.

Sign in / Sign up

Export Citation Format

Share Document