Experimental study of back gate bias effect and short channel effect in ultra-thin buried oxide tri-gate nanowire MOSFETs

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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Ground plane and selective buried oxide based planar junctionless transistor

Frequenz ◽

10.1515/freq-2021-0059 ◽

2021 ◽

Vol 0 (0) ◽

Author(s):

Asim M. Murshid ◽

Faisal Bashir

Keyword(s):

Electric Field ◽

Ground Plane ◽

Cutoff Frequency ◽

Volume Depletion ◽

Short Channel ◽

Short Channel Effect ◽

Buried Oxide ◽

Channel Effect ◽

Junctionless Transistor ◽

20 Nm

Abstract In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON/I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

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Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0106 ◽

2012 ◽

Author(s):

Yuk L. Tsang ◽

Xiang D. Wang ◽

Reyhan Ricklefs ◽

Jason Goertz

Keyword(s):

Threshold Voltage ◽

Electrical Characterization ◽

Cmos Technology ◽

Short Channel ◽

Visual Defect ◽

Subthreshold Region ◽

Short Channel Effect ◽

Channel Effect ◽

Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

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