A novel multi-level interconnect scheme with air as low K inter-metal dielectric for ultradeep submicron application

AbstractThis paper reports degradation characteristics of low-k dielectric (FOX) in multi-level metal structures (comb-type capacitors) submitted to moisture stress. A large increase of leakage current (>105) and capacitance (up to ×3) is observed after moisture stress when only FOX is used as lateral dielectric, while moderate degradation takes place when an oxide liner is placed between FOX and metal lines. Enhanced moisture induced degradation is found on previously probed dices with respect to virgin devices. Systematic electrical measurements, combined with SEM analysis, are performed to find out the moisture diffusion path. When contact pads are damaged by previous probing (owing to the mechanical weakness of FOX in the pad stack), they provide a direct entry path for enhanced humidity intake. Humidity is also shown to enter through wafer border. Using a SiO2 liner combined with FOX improves considerably the resistance to moisture degradation.

Download Full-text

Enhancement of adhesion strength of Cu layer on single and multi-layer dielectric film stack in Cu/low k multi-level interconnects

Microelectronic Engineering ◽

10.1016/j.mee.2004.05.003 ◽

2004 ◽

Vol 75 (2) ◽

pp. 183-193 ◽

Cited By ~ 5

Author(s):

S Balakumar ◽

Grace Wong ◽

Chi Fo Tsang ◽

T Hara ◽

W.J Yoo

Keyword(s):

Adhesion Strength ◽

Dielectric Film ◽

Multi Level ◽

Low K

Download Full-text

Via Electromigration Lifetime Improvement of Aluminum Dual-Damascene Interconnects by Using Soft Low-k Organic SOG Interlayer Dielectrics

MRS Proceedings ◽

10.1557/proc-612-d2.5.1 ◽

2000 ◽

Vol 612 ◽

Author(s):

Hisashi Kaneko ◽

Takamasa Usui ◽

Sachiyo Ito ◽

Masahiko Hasunuma

Keyword(s):

Tensile Stress ◽

Young’S Modulus ◽

Young's Modulus ◽

Void Nucleation ◽

Dielectric Materials ◽

Dual Damascene ◽

Atom Migration ◽

Multi Level ◽

Damascene Interconnects ◽

Low K

AbstractThe via electromigration(EM) reliability of aluminum(Al) dual-damascene interconnects by using Niobium(Nb) new reflow liner is described. It has been found that the via EM lifetime was improved by introducing low-k organic spin on glass(SOG)-passivated structure than the conventional TEOS-SiO2/SiN-passivated structure. Higher EM activation energy of 1.08 eV was obtained for the SOG-passivated structure than the conventional TEOS-passivated structure of 0.9 eV, even though no significant Al micro-crystal structure difference was found for both structures. It has been turned out that the low-k SOG material has the 1/7 Young's modulus (8 GPa) of TEOS-SiO2 (57 GPa) or thermal SiO2(70 GPa). The small Young's modulus means that SOG is more elastically deformable and/or softer than TEOS or thermal SiO2. This elastic deformation of the low-k SOG could retard the tensile stress evolution due to the Al atom migration near the cathode via, and elongated the time until the Al interconnect tensile stress exceeds the critical stress value for void nucleation. It has been concluded that the small-RC and reliable multi-level Al interconnect can be realized by the Nb-liner reflow-sputtered process with soft and low-k SOG dielectric materials.

Download Full-text

Integration Challenges of Inorganic Low-K (K≤2.5) Materials with CU for Sub-0.25μm Multilevel Interconnects

MRS Proceedings ◽

10.1557/proc-565-151 ◽

1999 ◽

Vol 565 ◽

Cited By ~ 2

Author(s):

K. C. Yu ◽

J. Defilippi ◽

R. Tiwari ◽

T. Sparks ◽

D. Smith ◽

...

Keyword(s):

Isothermal Annealing ◽

Process Development ◽

Cmos Technology ◽

Power Reduction ◽

Oxide Materials ◽

Power Devices ◽

Parametric Data ◽

Porous Oxide ◽

Multi Level ◽

Low K

AbstractThe recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

Download Full-text

CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects

MRS Proceedings ◽

10.1557/proc-0914-f12-07 ◽

2006 ◽

Vol 914 ◽

Cited By ~ 1

Author(s):

Patrick Leduc ◽

Thierry Farjot ◽

Mylène Savoye ◽

Anne-Cécile Demas ◽

Sylvain Maitrejean ◽

...

Keyword(s):

Elastic Properties ◽

Simple Correlation ◽

Fatigue Effect ◽

Cu Interconnects ◽

Level Number ◽

Number Increase ◽

Multi Level ◽

Low K

AbstractThis work shows that the addition of dielectric levels in interconnect stacks increases significantly the CMP-induced peeling. The fracture energies, measured by 4-point bending technique, are less sensitive to the level number increase, even if they are slightly degraded. This leads to the conclusion that delamination during polishing depends highly on the stack elastic properties and there is no simple correlation between stack adhesion and peeling during CMP. In this work, mechanical damages generated during CMP in the dielectric stack before peeling were also investigated. It was shown that, if no peeling appears, CMP have no effect on stack reliability. This indicates that negligible “fatigue” effect takes place during CMP.

Download Full-text