FUNCTIONAL PEARL Derivation of a logarithmic time carry lookahead addition circuit

2004 ◽  
Vol 14 (6) ◽  
pp. 697-713 ◽  
Author(s):  
JOHN T. O'DONNELL ◽  
GUDULA RÜNGER
Keyword(s):  
Partial Evaluation ◽  
Digital Circuit ◽  
Description Language ◽  
Correctness Proof ◽  
Function Representation ◽  
Symbolic Function ◽  
Ripple Carry Adder ◽  
Circuit Description ◽  
Associative Function

Using Haskell as a digital circuit description language, we transform a ripple carry adder that requires $O(n)$ time to add two $n$-bit words into a parallel carry lookahead adder that requires $O(\log n)$ time. The ripple carry adder uses a scan function to calculate carry bits, but this scan cannot be parallelized directly since it is applied to a non-associative function. Several techniques are applied in order to introduce parallelism, including partial evaluation and symbolic function representation. The derivation given here constitutes a semi-formal correctness proof, and it also brings out explicitly each of the ideas underlying the algorithm.

Glass, a language for analog and digital circuit description, and its environment

1989 ◽  
Vol 27 (1-5) ◽  
pp. 267-271 ◽  
Author(s):  
H. Oolman ◽  
M. Seutter ◽  
C. van Reeuwijk
Keyword(s):  
Digital Circuit ◽  
Circuit Description

scholarly journals Review of high-speed phase accumulator for direct digital frequency synthesizer

2020 ◽  
Vol 10 (4) ◽  
pp. 4008
Author(s):  
Abdulkareem Dawah Abbas
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Frequency Control ◽  
Control Word ◽  
Description Language ◽  
Flip Flop ◽  
Ripple Carry Adder ◽  
Field Programmable ◽  
Hardware Description ◽  
Prefix Adders

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

scholarly journals VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH

2020 ◽  
Vol 6 (6) ◽  
pp. 40-50
Author(s):  
Anuradha Sandi
Keyword(s):  
Full Adder ◽  
Propagation Delay ◽  
Digital Circuit ◽  
Digital Design ◽  
Look Ahead ◽  
Half Adder ◽  
Ripple Carry Adder ◽  
Vlsi System ◽  
Digital Circuit Designs ◽  
Time Required

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

scholarly journals Formal Verification of Three-Valued Digital Waveforms

2019 ◽  
Vol 26 (3) ◽  
pp. 332-350
Author(s):  
Nina Yu. Kutsak ◽  
Vladislav V. Podymov
Keyword(s):  
Formal Verification ◽  
Real Time ◽  
Temporal Logic ◽  
Circuit Design ◽  
Digital Circuit ◽  
Solution Technique ◽  
Digital Signals ◽  
Correctness Proof ◽  
Verification Problem ◽  
Correctness Checking

We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages. According to modern methodologies, a digital circuit design starts at high abstraction levels provided by hardware description languages (HDLs). One of essential steps of an HDLbased circuit design is an HDL code debug, similar to the same step of program development in means and importance. A popular way of an HDL code debug is based on extraction and analysis of a waveform, which is a collection of plots for digital signals: functional descriptions of value changes related to selected circuit places in real time. We propose mathematical means for automation of correctness checking for such waveforms based on notions and methods of formal verification against temporal logic formulae, and focus on such typical featues of HDL-related digital signals and corresponding (informal) properties, such as real time, three-valuededness, and presence of signal edges. The three-valuededness means that at any given time, besides basic logical values 0 and 1, a signal may have a special undefined value: one of the values 0 and 1, but which one of them is either not known, or not important. An edge point of a signal is a time point at which the signal changes its value. The main results are mathematical notions, propositions, and algorithms which allow to formalize and solve a formal verification problem for considered waveforms, including: definitions for signals and waveforms which the mentioned typical digital signal features; a temporal logic suitable for formalization of waveform correctness properties, and a related verification problem statement; a solution technique for the verification problem, which is based on reduction to signal transfromation and analysis; a corresponding verification algorithm together with its correctness proof and “reasonable” complexity bounds.

Design and Implementation of the Infrared Remote-Controlled Digital Clock Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 1266-1269
Author(s):  
Jun Yang ◽  
Hong Ye Li ◽  
Long Liu
Keyword(s):  
Simple Structure ◽  
Digital Circuit ◽  
Description Language ◽  
Digital Clock ◽  
Development Cycle ◽  
Short Development Cycle ◽  
Quartus Ii ◽  
Function Modules ◽  
Hardware Description ◽  
And Function

The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, alarm clock and temperature measuring. Besides, it has many advantages, including stable system , simple structure, short development cycle, fast speed and the strong usability.

Stratus: A procedural circuit description language based upon Python

2007 ◽  
Author(s):  
Sophie Belloeil ◽  
Damien Dupuis ◽  
Christian Masson ◽  
Jean-Paul Chaput ◽  
Habib Mehrez
Keyword(s):  
Description Language ◽  
Circuit Description

scholarly journals Implementation of Area optimized Low power Multiplication and Accumulation

2019 ◽  
Vol 9 (1) ◽  
pp. 2928-2932
Keyword(s):  
Low Power ◽  
Digital Circuits ◽  
Digital Signal ◽  
Digital Circuit ◽  
System Level ◽  
Combinational Circuits ◽  
Verilog Hdl ◽  
Description Language ◽  
Hardware Description ◽  
On Chip

There is number of computations involved at every stage in Digital Signal Processing (DSP). At every stage of computation we have addition and multiplication of the terms derived from previous and presents stages. The general computation incorporates the use of normal multiplication and addition, but the circuitry of normal multiplication and addition is lethargic i.e., it consumes more space on chip, consumes more power and the speed of computation is also low.These drawbacks can be avoided by switching to proposed method called Multiplication and Accumulation (MAC). Aim of this project is to develop an Area optimized Low power digital circuit for MAC (Multiply and Accumulate) operation. We develop the Verilog Hardware Description Language code for the various implementations of the MAC (Multiply and Accumulate) that is we try to avoid using multipliers and prefer to use the combinational circuits like multiplexers. These Verilog HDL codes will be simulated to check the functionality. Once we get the expected results we go for the implementation of the digital circuits. We analyze all the MAC digital circuits to find out the best digital circuit which consumes minimum area and power. The importance of MAC in FPGA designs is explained by some filter designs. We also give some suggestions on the system level solutions based on the MAC.

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