Efficient Charge Transport through a Metal Oxide Semiconductor in the Nanocomposite Film with Tris(2,2‘-bipyridine)ruthenium(II)

2007 ◽  
Vol 111 (31) ◽  
pp. 11636-11641 ◽  
Author(s):  
Koji Sone ◽  
Masahiro Teraguchi ◽  
Takashi Kaneko ◽  
Toshiki Aoki ◽  
Masayuki Yagi
Keyword(s):  
Metal Oxide ◽  
Charge Transport ◽  
Nanocomposite Film ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Efficient Charge

Charge transport and storage in ion implanted metal-oxide-semiconductor structures

1982 ◽  
Vol 10 (3) ◽  
pp. 349-356
Author(s):  
L. Augulis ◽  
L. Pranevičius ◽  
J. Vosylius
Keyword(s):  
Metal Oxide ◽  
Charge Transport ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Structures ◽  
And Storage ◽  
Ion Implanted

scholarly journals Strongly Correlated Charge Transport in Silicon Metal-Oxide-Semiconductor Field-Effect Transistor Quantum Dots

2018 ◽  
Vol 121 (2) ◽  
Author(s):  
M. Seo ◽  
P. Roulleau ◽  
P. Roche ◽  
D. C. Glattli ◽  
M. Sanquer ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Metal Oxide ◽  
Charge Transport ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Strongly Correlated ◽  
Effect Transistor

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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