Design of ultra‐low power AES encryption cores with silicon demonstration in SOTB CMOS process

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽

10.3390/electronics10070805 ◽

2021 ◽

Vol 10 (7) ◽

pp. 805

Author(s):

Shi Zuo ◽

Jianzhong Zhao ◽

Yumei Zhou

Keyword(s):

Low Power ◽

Current Efficiency ◽

Phase Noise ◽

Duty Cycle ◽

Semiconductor Manufacturing ◽

Figure Of Merit ◽

Room Temperature ◽

Cmos Process ◽

Ultra Low Power ◽

Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11020019 ◽

2021 ◽

Vol 11 (2) ◽

pp. 19

Author(s):

Francesco Centurelli ◽

Riccardo Della Sala ◽

Pietro Monsurrò ◽

Giuseppe Scotti ◽

Alessandro Trifiletti

Keyword(s):

Low Power ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Slew Rate ◽

Large Signal ◽

Output Stage ◽

Ultra Low Power ◽

Input Stage ◽

Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

2008 IEEE Radio Frequency Integrated Circuits Symposium ◽

10.1109/rfic.2008.4561386 ◽

2008 ◽

Cited By ~ 37

Author(s):

Emanuel Cohen ◽

Shmuel Ravid ◽

Dan Ritter

Keyword(s):

Low Power ◽

Cmos Process ◽

Phase Array ◽

60 Ghz ◽

Ultra Low Power

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A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

SN Applied Sciences ◽

10.1007/s42452-021-04402-0 ◽

2021 ◽

Vol 3 (4) ◽

Author(s):

S. Chrisben Gladson ◽

Adith Hari Narayana ◽

V. Thenmozhi ◽

M. Bhaskar

Keyword(s):

Low Power ◽

Ieee 802.15.4 ◽

Low Voltage ◽

Low Noise ◽

Low Noise Amplifier ◽

Cmos Process ◽

Process Technology ◽

Ultra Low Power ◽

Power Mode ◽

Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

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A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Electronics ◽

10.3390/electronics9060928 ◽

2020 ◽

Vol 9 (6) ◽

pp. 928 ◽

Cited By ~ 1

Author(s):

Taehoon Kim ◽

Sivasundar Manisankar ◽

Yeonbae Chung

Keyword(s):

Low Power ◽

Low Voltage ◽

Cost Effective ◽

Operating Mode ◽

Sleep Mode ◽

Cmos Process ◽

Operating Voltage ◽

Cross Point ◽

Ultra Low Power ◽

Static Ram

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

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A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

Journal of Circuits System and Computers ◽

10.1142/s021812661750027x ◽

2016 ◽

Vol 26 (02) ◽

pp. 1750027 ◽

Cited By ~ 2

Author(s):

Chia-Hung Chang ◽

Cihun-Siyong Alex Gong ◽

Jian-Chiun Liou ◽

Yu-Lin Tsou ◽

Feng-Lin Shiu ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Cmos Process ◽

Communication Services ◽

Ultra Low Power ◽

Resistive Feedback ◽

Mics Band ◽

Down Conversion ◽

Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

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Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876802 ◽

2002 ◽

Author(s):

A.-S. Porret ◽

T. Melly ◽

E.A. Vittoz ◽

C.C. Enz

Keyword(s):

Low Power ◽

Cmos Process ◽

Digital Cmos ◽

Ultra Low Power

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Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126619501226 ◽

2019 ◽

Vol 28 (07) ◽

pp. 1950122 ◽

Cited By ~ 2

Author(s):

Imen Ghorbel ◽

Fayrouz Haddad ◽

Wenceslas Rahajandraibe ◽

Mourad Loulou

Keyword(s):

Low Power ◽

Design Methodology ◽

Frequency Tuning ◽

Supply Voltage ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Ultra Low Power ◽

Trade Offs ◽

Process Measurements ◽

Lc Vco

A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

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Low-power integrated transmitter design using frequency multiplication techniques

e & i Elektrotechnik und Informationstechnik ◽

10.1007/s00502-020-00856-z ◽

2020 ◽

Author(s):

Markus Stadelmayer ◽

Tim Schumacher ◽

Thomas Faseth ◽

Harald Pretl

Keyword(s):

Low Power ◽

Radio Frequency ◽

Short Range ◽

Cmos Process ◽

Power Demand ◽

Frequency Multiplication ◽

Ultra Low Power ◽

Third Harmonic ◽

Harmonic Extraction ◽

Transmitter Design

Abstract This paper proposes an approach to employ frequency multiplication techniques like edge-combining and third harmonic extraction in ultra-low-power integrated transmitter design. The overall power demand of the transmitter is reduced by keeping operating frequency of its components low. For that reason, edge-combining and third harmonic extraction are integrated directly into a switched mode power amplifier. Hence, the radio frequency signal is generated just before it is fed to the antenna. This leads to a reduced power demand of the overall transmitter in comparison to conventional designs where the oscillator and other components are operated directly at the radio frequency. Within this paper we propose an amplifier that generates a 2.4 GHz carrier frequency from a ring oscillator running at a low 200 MHz resulting in a frequency multiplication factor of twelve. The exemplary design is targeted to be used in ultra-low-power short range applications. Hence, our simulations using extracted layout models show that the amplifier provides an output power of approximately -12 dBm at a supply voltage of 0.6 V while consuming 2.4 mW of power fully integrated in a 180 nm 1P6M CMOS process. This demonstrates that the proposed techniques are especially suitable for ultra-low-power transmitter in short range applications. That includes medical and body area network applications.

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