Wideband monolithic AGC amplifier for 400 Mbit/s optical repeaters using an advanced Si-bipolar IC technology, SICOS

1986 ◽  
Vol 22 (4) ◽  
pp. 188 ◽  
Author(s):  
T. Kinoshita ◽  
K. Yamashita ◽  
M. Maeda ◽  
T. Nakamura
Keyword(s):  
Ic Technology

Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps

2004 ◽  
Author(s):  
T. Zanon ◽  
W. Maly
Keyword(s):  
Geometric Characterization ◽  
Deformation Characteristics ◽  
Analysis Study ◽  
Preliminary Results ◽  
Failure Patterns ◽  
Yield Learning ◽  
Sram Memory ◽  
Viable Approach ◽  
Ic Technology

Abstract Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

Integration of IC technology with MEMS: Silicon+ technology for the future

2007 ◽  
Author(s):  
A.J. Walton ◽  
J.T.M. Stevenson ◽  
I. Underwood ◽  
J.G. Terry ◽  
S. Smith ◽  
...  
Keyword(s):  
Silicon Technology ◽  
The Future ◽  
Ic Technology

A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

2021 ◽  
Author(s):  
Sachin Bhat ◽  
Sounak Shaun Ghosh ◽  
Sourabh Kulkarni ◽  
Mingyu Li ◽  
Csaba Andras Moritz
Keyword(s):  
3D Ic ◽  
Wafer Scale ◽  
Fine Grained ◽  
Ic Technology

SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs

2021 ◽  
Author(s):  
Sachin Bhat ◽  
Mingyu Li ◽  
Shaun Ghosh ◽  
Sourabh Kulkarni ◽  
Csaba Andras Moritz
Keyword(s):  
3D Ics ◽  
Ic Technology

GaAs IC technology, circuits, and systems

2003 ◽  
Author(s):  
B.M. Welch ◽  
R.C. Eden ◽  
F.S. Lee
Keyword(s):  
Ic Technology

Technologies for creating radiation-resistant VLSI

2021 ◽  
Vol 14 (3) ◽  
pp. 16-22
Author(s):  
I. Zhuravleva ◽  
Elena Popova
Keyword(s):  
Cmos Technology ◽  
Space Structures ◽  
Oxygen Ions ◽  
Change Of State ◽  
Future Space ◽  
Space Programs ◽  
Radiation Resistant ◽  
Cmos Vlsi ◽  
Ic Technology

The technology of radiation-resistant CMOS VLSI is based on industrial IC technology. The design uses feedback circuits and guard rings to compensate for single effects of cosmic particles (SEE). In most critical cases, these influences in digital circuits lead to single faults (SEU), which temporarily disrupt the state of memory cells, to latching (SEL), and in the long term to a catastrophic change of state. Various space programs confirm great prospects for their use in future space structures. The article discusses the effects of using radiation-resistant CMOS technology, technology based on a silicon-on-sapphire structure, CMOS technology on an insulating substrate taking into account typical characteristics, SIMOX-SOI technology, which consists in separation by implantation of oxygen ions. In new designs of circuits, more advanced algorithms should be implemented for the future.

scholarly journals 2D In-Plane Sensitive Hall-Effect Sensor

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 711
Author(s):  
Siya Lozanova ◽  
Ivan Kolev ◽  
Avgust Ivanov ◽  
Chavdar Roumenin
Keyword(s):  
Hall Effect ◽  
Signal To Noise Ratio ◽  
Hall Effect Sensor ◽  
Orthogonal Components ◽  
The Mean ◽  
The Cross ◽  
The Magnetic Field ◽  
Outer Contact ◽  
Hall Elements ◽  
Ic Technology

A new 2D (two-dimensional) in-plane sensitive Hall-effect sensor comprising two identical n-Si Greek-crosses is presented. Each of the crosses contains one central square contact and, symmetrically to each of their four sides, an outer contact is available. Outer electrode from one configuration is connected with the respective opposite contact from the other configuration, thus forming four parallel three-contact (3C) Hall elements. These original connections provide pairs of opposite supply currents in each of the cross-Hall structure. Also the obligatory load resistors in the outer contacts of 3С Hall elements are replaced by internal resistances of crosses themselves. The samples have been implemented by IC technology, using four masks. The magnetic field is parallel to the structures’ plane. The couples of opposite contacts of each Greek-cross are the outputs for the two orthogonal components of the magnetic vector at sensitivities S ≈ 115 V/AT whereas the cross-talk is very promising, reaching no more than 2.4%. The mean lowest detected magnetic induction B at a supply current Is = 3 mA over the frequency range f ≤ 500 Hz at a signal to noise ratio equal to unity, is Bmin ≈ 14 μT.

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