scholarly journals Evaluation of circuit performance of T‐shaped tunnel FET

2020 ◽  
Vol 14 (5) ◽  
pp. 667-673
Author(s):  
Prabhat Kumar Dubey ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Circuit Performance ◽  
Tunnel Fet

Predicting Analog Circuit Performance Based on Importance of Uncertainties

2010 ◽  
Vol E93-C (6) ◽  
pp. 893-904
Author(s):  
Jin SUN ◽  
Kiran POTLURI ◽  
Janet M. WANG
Keyword(s):  
Analog Circuit ◽  
Circuit Performance

Analysis of AC-DC Converter Circuit Performance with Difference Piezoelectric Transducer Array Connection

2020 ◽  
Vol 12 (7) ◽  
Author(s):  
Nik Ahmad Zainal Abidin ◽  
◽  
Norkharziana Mohd Nayan ◽  
Azuwa Ali ◽  
N. A. Azli ◽  
...  
Keyword(s):  
Piezoelectric Transducer ◽  
Simulation Analysis ◽  
Piezoelectric Sensor ◽  
Transducer Array ◽  
Circuit Performance ◽  
Array Configuration ◽  
Full Wave ◽  
Bridge Rectifier ◽  
In Series ◽  
Parallel Voltage

This research presents a simulation analysis for the AC-DC converter circuit with a different configurations of the array connection of the piezoelectric sensor. The selection of AC-DC converter circuits is full wave bridge rectifier (FWBR), parallel SSHI (P-SSHI) and parallel voltage multiplier (PVM) with array configuration variation in series (S), parallel (P), series-parallel (SP) and parallel-series (PS). The system optimizes with different load configurations ranging from 10 kΩ to 1 MΩ. The best configuration of AC-DC converter with an appropriate array piezoelectric connection producing the optimum output of harvested power is presented. According to the simulation results, the harvested power produced by using P-SSHI converter connected with 3 parallel piezoelectric transducer array was 85.9% higher than for PVM and 15.88% higher than FWBR.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Erratum: Circuit performance of low temperature CMOS polysilicon TFT operational amplifiers

1993 ◽  
Vol 29 (8) ◽  
pp. 726
Author(s):  
H.-G. Yang ◽  
P. Migliorato ◽  
C. Reita ◽  
S. Fluxman
Keyword(s):  
Low Temperature ◽  
Operational Amplifiers ◽  
Circuit Performance ◽  
Polysilicon Tft

Sensitivity-based CMOS VLSI circuit performance optimisation

1995 ◽  
Vol 31 (22) ◽  
pp. 1918-1919
Author(s):  
P.J. Mather ◽  
P. Hallam ◽  
M. Brouwer
Keyword(s):  
Vlsi Circuit ◽  
Circuit Performance ◽  
Cmos Vlsi

Two-stage amplifier design based on experimental Line-Tunnel FET data

2019 ◽  
Author(s):  
Walter Goncalez Filho ◽  
Joao A. Martino ◽  
Roberto Rangel ◽  
Paula G. D. Agopian ◽  
Eddy Simoen ◽  
...  
Keyword(s):  
Two Stage ◽  
Tunnel Fet ◽  
Experimental Line ◽  
Amplifier Design
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