scholarly journals High-frequency properties of a graphene nanoribbon field-effect transistor

2008 ◽  
Vol 104 (11) ◽  
pp. 114505 ◽  
Author(s):  
M. Ryzhii ◽  
A. Satou ◽  
V. Ryzhii ◽  
T. Otsuji
Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.


2016 ◽  
Vol 13 (2) ◽  
pp. 39-50 ◽  
Author(s):  
Zheng Chen ◽  
Yiying Yao ◽  
Wenli Zhang ◽  
Dushan Boroyevich ◽  
Khai Ngo ◽  
...  

This article presents a 1,200-V, 120-A silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) phase-leg module capable of operating at 200°C ambient temperature. Paralleling six 20-A MOSFET bare dice for each switch, this module outperforms the commercial SiC modules in higher operating temperature and lower package parasitics at a comparable power rating. The module's high-temperature capability is validated through the extensive characterizations of the SiC MOSFET, as well as the careful selections of suitable packaging materials. Particularly, the sealed-step-edge technology is implemented on the direct-bonded-copper substrates to improve the module's thermal cycling lifetime. Though still based on the regular wire-bond structure, the module is able to achieve over 40% reduction in the switching loop inductance compared with a commercial SiC module by optimizing its internal layout. By further embedding decoupling capacitors directly on the substrates, the module also allows SiC MOSFETs to be switched twice faster with only one-third turn-off overvoltages compared with the commercial module.


2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Mathan Natarajamoorthy ◽  
Jayashri Subbiah ◽  
Nurul Ezaila Alias ◽  
Michael Loong Peng Tan

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.


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