Nanoscale shielded channel dual gate stack silicon on nothing junctionless transistor for improving short channel effect and analog performance

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

Download Full-text

Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance

Communications in Computer and Information Science - Smart Trends in Information Technology and Computer Communications ◽

10.1007/978-981-10-3433-6_4 ◽

2016 ◽

pp. 27-38 ◽

Cited By ~ 1

Author(s):

S. C. Wagaj ◽

Y. V. Chavan

Keyword(s):

Short Channel ◽

Short Channel Effect ◽

Nano Scale ◽

Channel Effect ◽

Analog Performance ◽

Dual Material

Download Full-text

Ground plane and selective buried oxide based planar junctionless transistor

Frequenz ◽

10.1515/freq-2021-0059 ◽

2021 ◽

Vol 0 (0) ◽

Author(s):

Asim M. Murshid ◽

Faisal Bashir

Keyword(s):

Electric Field ◽

Ground Plane ◽

Cutoff Frequency ◽

Volume Depletion ◽

Short Channel ◽

Short Channel Effect ◽

Buried Oxide ◽

Channel Effect ◽

Junctionless Transistor ◽

20 Nm

Abstract In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON/I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

Download Full-text

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0106 ◽

2012 ◽

Author(s):

Yuk L. Tsang ◽

Xiang D. Wang ◽

Reyhan Ricklefs ◽

Jason Goertz

Keyword(s):

Threshold Voltage ◽

Electrical Characterization ◽

Cmos Technology ◽

Short Channel ◽

Visual Defect ◽

Subthreshold Region ◽

Short Channel Effect ◽

Channel Effect ◽

Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Download Full-text